公开(公告)号：US07902553B2

公开(公告)日：2011-03-08

申请号：US11930536

申请日：2007-10-31

申请人： Byoung-June Kim ,  Jae-Ho Choi ,  Chang-Oh Jeong ,  Sung-Hoon Yang ,  Je-Hun Lee ,  Do-Hyun Kim ,  Hwa-Yeul Oh ,  Yong-Mo Choi

发明人： Byoung-June Kim ,  Jae-Ho Choi ,  Chang-Oh Jeong ,  Sung-Hoon Yang ,  Je-Hun Lee ,  Do-Hyun Kim ,  Hwa-Yeul Oh ,  Yong-Mo Choi

IPC分类号： H01L29/04

CPC分类号： H01L27/1255 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66765

摘要： A manufacturing method of a thin film transistor (TFT) includes forming a gate electrode including a metal that can be combined with silicon to form silicide on a substrate and forming a gate insulation layer by supplying a gas which includes silicon to the gate electrode at a temperature below about 280° C. The method further includes forming a semiconductor on the gate insulation layer, forming a data line and a drain electrode on the semiconductor and forming a pixel electrode connected to the drain electrode.

摘要翻译： 薄膜晶体管（TFT）的制造方法包括形成包括可以与硅组合的金属的栅电极，以在衬底上形成硅化物，并通过在栅极电极中向栅电极提供包括硅的气体形成栅极绝缘层 该方法还包括在栅极绝缘层上形成半导体，在半导体上形成数据线和漏极并形成连接到漏电极的像素电极。

公开(公告)号：US20100283050A1

公开(公告)日：2010-11-11

申请号：US12774255

申请日：2010-05-05

申请人： Je-hun Lee ,  Dong-ju Yang ,  Tae-hyung Ihn ,  Do-hyun Kim ,  Sun-young Hong ,  Seung-jae Jung ,  Chang-oh Jeong ,  Eun-guk Lee

发明人： Je-hun Lee ,  Dong-ju Yang ,  Tae-hyung Ihn ,  Do-hyun Kim ,  Sun-young Hong ,  Seung-jae Jung ,  Chang-oh Jeong ,  Eun-guk Lee

IPC分类号： H01L33/00 ,  H01L29/786

CPC分类号： H01L29/7869

摘要： Provided is a method of fabricating a semiconductive oxide thin-film transistor (TFT) substrate. The method includes forming gate wiring on an insulation substrate; and forming a structure in which a semiconductive oxide film pattern and data wiring are stacked on the gate wiring, wherein the semiconductive oxide film pattern is selectively patterned to have channel regions of first thickness and source/drain regions of greater second thickness and where image data is coupled to the source regions by data wiring formed on the source regions. According to a 4-mask embodiment, the data wiring and semiconductive oxide film pattern are defined by a shared etch mask.

摘要翻译： 提供一种制造半导体氧化物薄膜晶体管（TFT）衬底的方法。 该方法包括在绝缘基板上形成栅极布线; 并且形成其中半导体氧化物膜图案和数据布线堆叠在栅极布线上的结构，其中半导体氧化物膜图案被选择性地图案化以具有第二厚度的第一厚度的沟道区域和源极/漏极区域，并且其中图像数据 通过形成在源极区域上的数据布线耦合到源极区域。 根据4掩模实施例，数据布线和半导体氧化膜图案由共享蚀刻掩模限定。

公开(公告)号：US20100276686A1

公开(公告)日：2010-11-04

申请号：US12756323

申请日：2010-04-08

申请人： Dong-Hoon Lee ,  Je-Hun Lee ,  Do-Hyun Kim ,  Hee-Tae Kim ,  Chang-Oh Jeong ,  Pil-Sang Yun ,  Ki-Won Kim

发明人： Dong-Hoon Lee ,  Je-Hun Lee ,  Do-Hyun Kim ,  Hee-Tae Kim ,  Chang-Oh Jeong ,  Pil-Sang Yun ,  Ki-Won Kim

IPC分类号： H01L29/786 ,  H01L29/12 ,  H01L21/336

CPC分类号： H01L27/1225 ,  H01L27/1214 ,  H01L27/1288 ,  H01L29/7869

摘要： A thin film transistor (TFT) substrate and a method of fabricating the same are provided. The thin film transistor substrate may have low resistance characteristics and may have reduced mutual diffusion and contact resistance between an active layer pattern and data wiring. The thin film transistor substrate may include gate wiring formed on an insulating substrate. Oxide active layer patterns may be formed on the gate wiring and may include a first substance. Data wiring may be formed on the oxide active layer patterns to cross the gate wiring and may include a second substance. Barrier layer patterns may be disposed between the oxide active layer patterns and the data wiring and may include a third substance.

摘要翻译： 提供薄膜晶体管（TFT）基板及其制造方法。 薄膜晶体管基板可以具有低电阻特性，并且可以减少有源层图案和数据布线之间的相互扩散和接触电阻。 薄膜晶体管基板可以包括形成在绝缘基板上的栅极布线。 氧化物有源层图案可以形成在栅极布线上，并且可以包括第一物质。 数据布线可以形成在氧化物有源层图案上以跨越栅极布线，并且可以包括第二物质。 阻挡层图案可以设置在氧化物活性层图案和数据布线之间，并且可以包括第三物质。

公开(公告)号：US07811868B2

公开(公告)日：2010-10-12

申请号：US11932233

申请日：2007-10-31

申请人： Do-Hyun Kim ,  Won-Suk Shin ,  Chang-Oh Jeong ,  Hong-Sick Park ,  Eun-Guk Lee ,  Je-Hun Lee

发明人： Do-Hyun Kim ,  Won-Suk Shin ,  Chang-Oh Jeong ,  Hong-Sick Park ,  Eun-Guk Lee ,  Je-Hun Lee

IPC分类号： H01L21/768

CPC分类号： H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/458

摘要： A method for manufacturing a thin film transistor array panel includes forming a gate line on a substrate; sequentially forming a gate insulating layer, a silicon layer, and a conductor layer including a lower layer and an upper layer on the gate line, forming a photoresist film, on the conductor layer, patterning the photoresist film to form a photoresist pattern including a first portion and a second portion having a greater thickness than the first portion, etching the upper layer and the lower layer by using the photoresist pattern as art etch mask, etching the silicon layer by using the photoresist pattern as an etch mask to form a semiconductor, removing the second portion of the photoresist pattern by using an etch back process, selectively wet-etching the upper layer of the conductor layer by using the photoresist pattern as an etch mask, dry-etching the lower layer of the conductor layer by using the photoresist pattern as an etch mask to form a data line and a drain electrode including remaining upper and lower layers, and forming a pixel electrode connected to the drain electrode.

摘要翻译： 一种制造薄膜晶体管阵列面板的方法，包括在基板上形成栅极线; 在栅极线上顺序地形成栅极绝缘层，硅层和包括下层和上层的导体层，在导体层上形成光致抗蚀剂膜，图案化光致抗蚀剂膜以形成包括第一 部分和第二部分具有比第一部分更大的厚度，通过使用光致抗蚀剂图案作为蚀刻掩模蚀刻上层和下层，通过使用光致抗蚀剂图案作为蚀刻掩模来蚀刻硅层以形成半导体， 通过使用回蚀工艺去除光致抗蚀剂图案的第二部分，通过使用光致抗蚀剂图案作为蚀刻掩模来选择性地湿法蚀刻导体层的上层，通过使用光致抗蚀剂干蚀刻导体层的下层 图案作为蚀刻掩模以形成包括剩余的上层和下层的数据线和漏极，并且形成连接到漏电极的像素电极 。

公开(公告)号：US20100150278A1

公开(公告)日：2010-06-17

申请号：US12561076

申请日：2009-09-16

申请人： Il-Gu Lee ,  Hyun-Gu Park ,  Je-Hun Lee ,  Sok-Kyu Lee

发明人： Il-Gu Lee ,  Hyun-Gu Park ,  Je-Hun Lee ,  Sok-Kyu Lee

IPC分类号： H04B1/06 ,  H04L27/06

CPC分类号： H04W52/028 ,  H04L2027/0016 ,  H04L2027/0067 ,  H04W52/0245 ,  Y02D70/142

摘要： An apparatus for reducing power consumption of a receiver in a high-speed wireless communication system and a control method thereof are provided. The apparatus for processing a signal in a receiver of a wireless communication system includes a carrier sensor configured to sense a carrier used in the wireless communication system, a decoder configured to decode the detected carrier signal to a signal and data, and a controller configured to control supplying power and a clock only to the carrier sensor during carrier sensing, and supplying power and a clock to an overall receiver when a carrier is sensed.

摘要翻译： 提供一种用于降低高速无线通信系统中的接收机的功耗的装置及其控制方法。 用于处理无线通信系统的接收机中的信号的装置包括被配置为感测在无线通信系统中使用的载波的载波传感器，被配置为将检测到的载波信号解码为信号和数据的解码器，以及控制器， 在载波检测期间仅控制向载波传感器提供功率和时钟，并且当检测到载波时，向整个接收机提供功率和时钟。

公开(公告)号：US07682882B2

公开(公告)日：2010-03-23

申请号：US12153674

申请日：2008-05-22

申请人： Myung-kwan Ryu ,  Sang-yoon Lee ,  Je-hun Lee ,  Tae-sang Kim ,  Jang-yeon Kwon ,  Kyung-bae Park ,  Kyung-seok Son ,  Ji-sim Jung

发明人： Myung-kwan Ryu ,  Sang-yoon Lee ,  Je-hun Lee ,  Tae-sang Kim ,  Jang-yeon Kwon ,  Kyung-bae Park ,  Kyung-seok Son ,  Ji-sim Jung

IPC分类号： H01L21/00

CPC分类号： H01L29/7869

摘要： Provided is a method of manufacturing a ZnO-based thin film transistor (TFT). The method may include forming source and drain electrodes using one or two wet etchings. A tin (Sn) oxide, a fluoride, or a chloride having relatively stable bonding energy against plasma may be included in a channel layer. Because the source and drain electrodes are formed by wet etching, damage to the channel layer and an oxygen vacancy may be prevented or reduced. Because the material having higher bonding energy is distributed in the channel layer, damage to the channel layer occurring when a passivation layer is formed may be prevented or reduced.

摘要翻译： 提供了一种制造ZnO基薄膜晶体管（TFT）的方法。 该方法可以包括使用一个或两个湿蚀刻来形成源极和漏极。 对于等离子体具有相对稳定的结合能的锡（Sn）氧化物，氟化物或氯化物可以包括在通道层中。 因为源电极和漏电极是通过湿蚀刻形成的，所以可以防止或减少对沟道层的损伤和氧空位。 因为具有较高结合能的材料分布在沟道层中，所以可以防止或减少在形成钝化层时对沟道层的损坏。

公开(公告)号：US20100051933A1

公开(公告)日：2010-03-04

申请号：US12500506

申请日：2009-07-09

申请人： Do-Hyun Kim ,  Je-Hun Lee ,  Pil-Sang Yun ,  Dong-Hoon Lee ,  Bong-Kyun Kim

发明人： Do-Hyun Kim ,  Je-Hun Lee ,  Pil-Sang Yun ,  Dong-Hoon Lee ,  Bong-Kyun Kim

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/1225 ,  H01L29/7869

摘要： A thin film transistor array substrate having a high charge mobility and that can raise a threshold voltage, and a method of fabricating the thin film transistor array substrate are provided. The thin film transistor array substrate includes: an insulating substrate; a gate electrode formed on the insulating substrate; an oxide semiconductor layer comprising a lower oxide layer formed on the gate electrode and an upper oxide layer formed on the lower oxide layer, such that the oxygen concentration of the upper oxide layer is higher than the oxygen concentration of the lower oxide layer; and a source electrode and a drain electrode formed on the oxide semiconductor layer and separated from each other.

摘要翻译： 提供具有高电荷迁移率并且可以提高阈值电压的薄膜晶体管阵列基板，以及制造薄膜晶体管阵列基板的方法。 薄膜晶体管阵列基板包括：绝缘基板; 形成在所述绝缘基板上的栅电极; 氧化物半导体层，其包括形成在所述栅电极上的低氧化物层和形成在所述低氧化物层上的上氧化物层，使得所述上氧化物层的氧浓度高于所述低氧化物层的氧浓度; 以及形成在氧化物半导体层上并且彼此分离的源电极和漏电极。

公开(公告)号：US20090224254A1

公开(公告)日：2009-09-10

申请号：US12417280

申请日：2009-04-02

申请人： Je-Hun LEE ,  Sung-Jin Kim ,  Hee-Joon Kim ,  Chang-Oh Jeong

发明人： Je-Hun LEE ,  Sung-Jin Kim ,  Hee-Joon Kim ,  Chang-Oh Jeong

IPC分类号： H01L27/06 ,  H01L33/00 ,  H01L29/786

CPC分类号： G02F1/13439 ,  G02F1/13458 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908

摘要： A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn in which the rmetal component is reduced in the IZO, ITO, or a-ITO is not produced on the surfaces of the common electrode.

摘要翻译： 提供了薄膜晶体管阵列面板，其包括基板，形成在基板上的多个栅极线，在基板上具有透明导电层的多个公共电极，覆盖栅极线和公共电极的栅极绝缘层 形成在所述栅极绝缘层上的多个半导体层，形成在所述半导体层和所述栅极绝缘层上的多个源极电极的多条数据线，形成在所述半导体层上的多个漏电极和所述栅极绝缘体 并且与公共电极重叠并连接到漏电极的多个像素电极。 由于公共电极由ITON，IZON或者-IONON制成，或者是将双重层的ITO / ITON，IZO / IZON或者a-ITO / a-ITON，当注入H 2或SiH 4以形成氮化硅时 SiNX）层，在公共电极的表面上不产生在IZO，ITO或ITO中还原金属成分的不透明金属Sn或Zn。

公开(公告)号：US20090174835A1

公开(公告)日：2009-07-09

申请号：US12344075

申请日：2008-12-24

申请人： Je-Hun Lee ,  Do-Hyun Kim ,  Tae-Sang Kim ,  Kyung-Seok Son ,  Chang-Oh Jeong

发明人： Je-Hun Lee ,  Do-Hyun Kim ,  Tae-Sang Kim ,  Kyung-Seok Son ,  Chang-Oh Jeong

IPC分类号： G02F1/1368 ,  H01L21/70 ,  H01L27/12

CPC分类号： H01L33/0095 ,  G02F1/133512 ,  G02F1/133516 ,  G02F1/136209 ,  G02F1/1368 ,  G02F2001/133397 ,  G02F2001/136222 ,  G02F2001/136231 ,  G02F2001/13685 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/458

摘要： A liquid crystal display (LCD) includes thin film transistors (TFTs) each having spaced apart source/drain electrodes and an oxide-type semiconductive film disposed over and between the source/drain electrodes to define an active layer. Each of the source/drain electrodes includes a portion of a subdivided transparent conductive layer where one subdivision of the transparent conductive layer continues from within its one of the source/drain electrodes to define an optically exposed pixel-electrode that is reliably connected integrally to the one source/drain electrode. Mass production costs can be reduced and production reliability increased because a fewer number of photolithographic masks can be used to form the TFTs.

摘要翻译： 液晶显示器（LCD）包括薄膜晶体管（TFT），每个薄膜晶体管具有间隔开的源/漏电极和设置在源/漏电极之间和之间的氧化物型半导体膜，以限定有源层。 源/漏电极中的每一个包括细分透明导电层的一部分，其中透明导电层的一个细分从其源极/漏极之一内延伸，以限定光学曝光的像素电极，其可靠地与 一个源/漏电极。 由于可以使用较少数量的光刻掩模来形成TFT，所以可以降低批量生产成本并提高生产可靠性。

公开(公告)号：US07524706B2

公开(公告)日：2009-04-28

申请号：US11844597

申请日：2007-08-24

申请人： Je Hun Lee ,  Yang Ho Bae ,  Beom Seok Cho ,  Chang Oh Jeong

发明人： Je Hun Lee ,  Yang Ho Bae ,  Beom Seok Cho ,  Chang Oh Jeong

IPC分类号： H01L21/00

CPC分类号： H01L29/458 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288

摘要： A thin film transistor array panel includes a source electrode and a drain electrode composed of a Mo alloy layer and a Cu layer, and an alloying element of the Mo alloy layer forms a nitride layer as a diffusion barrier against the Cu layer. The nitride layer can be formed between the Mo alloy layer and the Cu layer, between the Mo alloy layer and the semiconductor layer or in the Mo alloy layer. A method of fabricating a thin film transistor array panel includes forming a data line having a first conductive layer and a second conductive layer, the first conductive layer containing a Mo alloy and the second conductive layer containing Cu, and performing a nitrogen treatment so that an alloying element in the first conductive layer forms a nitride layer. The nitrogen treatment can be performed before forming the first conductive layer, after forming the first conductive layer, or during forming the first conductive layer.

摘要翻译： 薄膜晶体管阵列面板包括由Mo合金层和Cu层构成的源电极和漏电极，Mo合金层的合金元素形成氮化物层作为对Cu层的扩散阻挡层。 可以在Mo合金层和Cu层之间，Mo合金层和半导体层之间或Mo合金层中形成氮化物层。 制造薄膜晶体管阵列面板的方法包括：形成具有第一导电层和第二导电层的数据线，所述第一导电层含有Mo合金，所述第二导电层含有Cu，并进行氮处理，使得 第一导电层中的合金元素形成氮化物层。 在形成第一导电层之前，在形成第一导电层之后，或者在形成第一导电层期间，可以进行氮处理。