公开(公告)号：US08119480B2

公开(公告)日：2012-02-21

申请号：US12923593

申请日：2010-09-29

申请人： Sung-Hoon Lee ,  Sungil Park ,  Young-Gu Jin ,  Jongseob Kim ,  Ki-Ha Hong

发明人： Sung-Hoon Lee ,  Sungil Park ,  Young-Gu Jin ,  Jongseob Kim ,  Ki-Ha Hong

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  G11C16/10 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/66833

摘要： A semiconductor memory device performing an erase operation using an erase gate and a method of manufacturing the same are provided. The memory device may include a charge trap layer storing a first charge transfer medium having a first polarity and at least one erase gate. The at least one erase gate may be formed below the charge trap layer. A second charge transfer medium, which has a second polarity opposite to the first polarity, may be stored in the at least one erase gate. During the erase operation, the second charge transfer medium migrates to the charge trap layer causing the first charge transfer medium to combine with the second charge transfer medium.

摘要翻译： 提供了使用擦除栅极执行擦除操作的半导体存储器件及其制造方法。 存储器件可以包括存储具有第一极性的第一电荷转移介质和至少一个擦除栅极的电荷陷阱层。 至少一个擦除栅极可以形成在电荷陷阱层下面。 具有与第一极性相反的第二极性的第二电荷转移介质可以存储在至少一个擦除栅中。 在擦除操作期间，第二电荷转移介质迁移到电荷捕获层，使得第一电荷转移介质与第二电荷转移介质组合。

公开(公告)号：US20110303952A1

公开(公告)日：2011-12-15

申请号：US13151475

申请日：2011-06-02

申请人： In-jun Hwang ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  Ki-ha Hong

发明人： In-jun Hwang ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  Ki-ha Hong

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/778 ,  H01L29/0847 ,  H01L29/1029 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7785 ,  H01L29/7786

摘要： A High electron mobility transistor (HEMT) includes a source electrode, a gate electrode, a drain electrode, a channel forming layer in which a two-dimensional electron gas (2DEG) channel is induced, and a channel supplying layer for inducing the 2DEG channel in the channel forming layer. The source electrode and the drain electrode are located on the channel supplying layer. A channel increase layer is between the channel supplying layer and the source and drain electrodes. A thickness of the channel supplying layer is less than about 15 nm.

摘要翻译： 高电子迁移率晶体管（HEMT）包括源电极，栅电极，漏电极，其中感应二维电子气（2DEG）沟道的沟道形成层，以及用于诱导2DEG沟道的沟道供应层 在通道形成层中。 源电极和漏极位于沟道供给层上。 通道增加层位于通道供应层和源极和漏极之间。 沟道供应层的厚度小于约15nm。

公开(公告)号：US20110273221A1

公开(公告)日：2011-11-10

申请号：US13064264

申请日：2011-03-15

申请人： Ho-jung Kim ,  Jae-kwang Shin ,  Jae-Joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  In-jun Hwang ,  Ki-ha Hong

发明人： Ho-jung Kim ,  Jae-kwang Shin ,  Jae-Joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  In-jun Hwang ,  Ki-ha Hong

IPC分类号： H03K17/284 ,  H03K17/687

CPC分类号： H03K17/163 ,  H03K17/284

摘要： A power device includes a switching device having a control terminal and an output terminal; and a driving circuit configured to provide a driving voltage to the control terminal such that a voltage between the control terminal and the output terminal remains less than or equal to a critical voltage. A rise time required for the driving voltage to reach a target level is determined according to current-voltage characteristics of the switching device. And, when the voltage between the control terminal and the output terminal exceeds the critical voltage, leakage current is generated between the control terminal and the output terminal.

摘要翻译： 功率器件包括具有控制端子和输出端子的开关器件; 以及驱动电路，被配置为向控制端子提供驱动电压，使得控制端子和输出端子之间的电压保持小于或等于临界电压。 根据开关装置的电流 - 电压特性来确定驱动电压达到目标电平所需的上升时间。 而且，当控制端子与输出端子之间的电压超过临界电压时，控制端子与输出端子之间产生漏电流。

公开(公告)号：US20110272743A1

公开(公告)日：2011-11-10

申请号：US13096573

申请日：2011-04-28

申请人： In-jun Hwang ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  Ki-ha Hong

发明人： In-jun Hwang ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  Ki-ha Hong

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/778 ,  H01L21/28008 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/42364 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

摘要： High electron mobility transistors (HEMTs) including lightly doped drain (LDD) regions and methods of manufacturing the same. A HEMT includes a source, a drain, a gate, a channel supplying layer for forming at least a 2-dimensional electron gas (2DEG) channel, and a channel formation layer in which at least the 2DEG channel is formed. The channel supplying layer includes a plurality of semiconductor layers having different polarizabilities. A portion of the channel supplying layer is recessed. One of the plurality of semiconductor layers, which is positioned below an uppermost layer is an etching buffer layer, as well as a channel supplying layer.

摘要翻译： 包括轻掺杂漏极（LDD）区域的高电子迁移率晶体管（HEMT）及其制造方法。 HEMT包括源极，漏极，栅极，用于形成至少二维电子气（2DEG）沟道的沟道供应层，以及至少形成2DEG通道的沟道形成层。 通道供给层包括具有不同极化率的多个半导体层。 通道供应层的一部分凹进。 位于最上层下方的多个半导体层中的一个是蚀刻缓冲层，以及沟道供给层。

公开(公告)号：US20110221482A1

公开(公告)日：2011-09-15

申请号：US12923857

申请日：2010-10-12

申请人： Ho-jung Kim ,  Jong-seob Kim ,  Jai-Kwang Shin ,  Jae-joon Oh ,  Ki-ha Hong ,  In-jun Hwang ,  Hyuk-soon Choi

发明人： Ho-jung Kim ,  Jong-seob Kim ,  Jai-Kwang Shin ,  Jae-joon Oh ,  Ki-ha Hong ,  In-jun Hwang ,  Hyuk-soon Choi

IPC分类号： H03K3/01 ,  H03K17/00

CPC分类号： H03K17/6871 ,  H02M1/08 ,  H02M3/158 ,  H02M3/337 ,  H02M2001/0074 ,  H03K2217/0081

摘要： Provided is a semiconductor device that may include a switching device having a negative threshold voltage, and a driving unit between a power terminal and a ground terminal and providing a driving voltage for driving the switching device. The switching device may be connected to a virtual ground node having a virtual ground voltage that is greater than a ground voltage supplied from the ground terminal and may be turned on when a difference between the driving voltage and the virtual ground voltage is greater than the negative threshold voltage.

摘要翻译： 提供一种半导体器件，其可以包括具有负阈值电压的开关器件，以及电源端子和接地端子之间的驱动单元，并且提供用于驱动开关器件的驱动电压。 开关器件可以连接到具有大于从接地端子提供的接地电压的虚拟接地电压的虚拟接地节点，并且当驱动电压和虚拟接地电压之间的差大于负值时，可以导通 阈值电压。

公开(公告)号：US20110210751A1

公开(公告)日：2011-09-01

申请号：US13065000

申请日：2011-05-02

申请人： Ki-ha Hong ,  Hyuk-soon Choi ,  Jong-seob Kim ,  Jai-kwang Shin

发明人： Ki-ha Hong ,  Hyuk-soon Choi ,  Jong-seob Kim ,  Jai-kwang Shin

IPC分类号： G01R27/00

CPC分类号： G01N29/036 ,  G01N2291/0257 ,  Y10S977/957

摘要： Provided is a chemical sensor that may include a first electrode on a substrate, a sensing member covering the first electrode on the substrate, and a plurality of second electrodes on a surface of the sensing member exposing the surface of the sensing member. The chemical sensor may be configured to measure the change in electrical characteristics when a compound to be sensed is adsorbed on the sensing member. Provided also is a chemical sensor array including an array of chemical sensors.

公开(公告)号：US08004906B2

公开(公告)日：2011-08-23

申请号：US12805498

申请日：2010-08-03

申请人： Ki-ha Hong ,  Sung-hoon Lee ,  Jae-woong Hyun ,  Jai-kwang Shin ,  Young-gu Jin ,  Sung-il Park ,  Jong-seob Kim

发明人： Ki-ha Hong ,  Sung-hoon Lee ,  Jae-woong Hyun ,  Jai-kwang Shin ,  Young-gu Jin ,  Sung-il Park ,  Jong-seob Kim

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： Provided is a method of reliably operating a highly integratable nonvolatile memory device. The nonvolatile memory device may include a string selection transistor, a plurality of memory transistors, and a ground selection transistor between a bit line and a common source line. In the nonvolatile memory device, data may be erased from the memory transistors by applying an erasing voltage to the bit line or the common source line.

摘要翻译： 提供了可靠地操作高度可积分的非易失性存储器件的方法。 非易失性存储器件可以包括串选择晶体管，多个存储晶体管和位线和公共源极线之间的接地选择晶体管。 在非易失性存储器件中，通过向位线或公共源极线施加擦除电压，可以从存储晶体管擦除数据。

公开(公告)号：US07978006B2

公开(公告)日：2011-07-12

申请号：US12585724

申请日：2009-09-23

申请人： Jai-kwang Shin ,  Sun-ae Seo ,  Jong-seob Kim ,  Ki-ha Hong ,  Hyun-jong Chung

发明人： Jai-kwang Shin ,  Sun-ae Seo ,  Jong-seob Kim ,  Ki-ha Hong ,  Hyun-jong Chung

IPC分类号： H01L25/00

CPC分类号： H01L29/7613 ,  B82Y10/00 ,  H01L29/1029 ,  H01L29/16 ,  H01L29/1606 ,  H01L29/66977

摘要： A quantum interference transistor may include a source; a drain; N channels (N≧2), between the source and the drain, and having N−1 path differences between the source and the drain; and at least one gate disposed at one or more of the N channels. One or more of the N channels may be formed in a graphene sheet. A method of manufacturing the quantum interference transistor may include forming one or more of the N channels using a graphene sheet. A method of operating the quantum interference transistor may include applying a voltage to the at least one gate. The voltage may shift a phase of a wave of electrons passing through a channel at which the at least one gate is disposed.

摘要翻译： 量子干涉晶体管可以包括源极; 排水 在源极和漏极之间的N沟道（N≥2），源极和漏极之间具有N-1个路径差; 以及设置在所述N个通道中的一个或多个的至少一个门。 N个通道中的一个或多个可以形成在石墨烯片中。 制造量子干涉晶体管的方法可以包括使用石墨烯片形成N个通道中的一个或多个。 操作量子干涉晶体管的方法可以包括向至少一个栅极施加电压。 电压可以使通过通道的电子的波的相位偏移至设置至少一个栅极的通道。

公开(公告)号：US20110021014A1

公开(公告)日：2011-01-27

申请号：US12923593

申请日：2010-09-29

申请人： Sung-Hoon Lee ,  Sungil Park ,  Young-Gu Jin ,  Jongseob Kim ,  Ki-Ha Hong

发明人： Sung-Hoon Lee ,  Sungil Park ,  Young-Gu Jin ,  Jongseob Kim ,  Ki-Ha Hong

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  G11C16/10 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/66833

摘要： A semiconductor memory device performing an erase operation using an erase gate and a method of manufacturing the same are provided. The memory device may include a charge trap layer storing a first charge transfer medium having a first polarity and at least one erase gate. The at least one erase gate may be formed below the charge trap layer. A second charge transfer medium, which has a second polarity opposite to the first polarity, may be stored in the at least one erase gate. During the erase operation, the second charge transfer medium migrates to the charge trap layer causing the first charge transfer medium to combine with the second charge transfer medium.

摘要翻译： 提供了使用擦除栅极执行擦除操作的半导体存储器件及其制造方法。 存储器件可以包括存储具有第一极性的第一电荷转移介质和至少一个擦除栅极的电荷陷阱层。 至少一个擦除栅极可以形成在电荷陷阱层下面。 具有与第一极性相反的第二极性的第二电荷转移介质可以存储在至少一个擦除栅中。 在擦除操作期间，第二电荷转移介质迁移到电荷捕获层，使得第一电荷转移介质与第二电荷转移介质组合。

公开(公告)号：US20100151659A1

公开(公告)日：2010-06-17

申请号：US12588828

申请日：2009-10-29

申请人： Ki-ha Hong ,  Kyoung-won Park ,  Jai-kwang Shin ,  Jong-seob Kim ,  Hyuk-soon Choi

发明人： Ki-ha Hong ,  Kyoung-won Park ,  Jai-kwang Shin ,  Jong-seob Kim ,  Hyuk-soon Choi

IPC分类号： H01L21/20 ,  B29C65/00 ,  B32B38/04 ,  B32B38/10 ,  H01L21/302

CPC分类号： H01L29/125 ,  B82Y10/00 ,  H01L29/127 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78696 ,  Y10T156/10 ,  Y10T156/1082

摘要： Example embodiments relate to a method of forming a core-shell structure. According to a method, a region in which the core-shell structure will be formed is defined on a substrate, and a core and a shell layer may be sequentially stacked in the defined region. A first shell layer may further be formed between the substrate and the core. When the core and the shell layer are sequentially stacked in the core-shell region, the method may further include forming a groove on the substrate, forming the first shell layer covering surfaces of the groove, forming the core in the groove of which surfaces are covered by the first shell layer, and forming a second shell layer covering the core.

摘要翻译： 示例性实施例涉及形成核 - 壳结构的方法。 根据一种方法，在基板上限定形成芯 - 壳结构的区域，并且可以在限定区域中顺序堆叠芯层和壳层。 第一壳层可以进一步形成在衬底和芯之间。 当核心层和壳层依次层叠在芯 - 壳区域中时，该方法还可以包括在基板上形成凹槽，形成覆盖凹槽表面的第一壳层，在其表面的凹槽中形成芯 被第一壳层覆盖，并且形成覆盖芯的第二壳层。