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    LOW CURRENT SWITCHING MAGNETIC TUNNEL JUNCTION DESIGN FOR MAGNETIC MEMORY USING DOMAIN WALL MOTION
    52.
    发明申请
    LOW CURRENT SWITCHING MAGNETIC TUNNEL JUNCTION DESIGN FOR MAGNETIC MEMORY USING DOMAIN WALL MOTION 有权
    使用域墙运动的磁流记忆的低电流开关磁通连接设计

    公开(公告)号：US20090109739A1

    公开(公告)日：2009-04-30

    申请号：US12255624

    申请日：2008-10-21

    Applicant: Rajiv Yadav RANJAN ,  Roger Klaus Malmhall ,  Parviz Keshtbod

    Inventor： Rajiv Yadav RANJAN ,  Roger Klaus Malmhall ,  Parviz Keshtbod

    IPC: G11C11/02

    CPC classification number: H01L27/222 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C19/0808 ,  H01L43/08

    Abstract: A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains within the free layer, creating a free layer domain wall. A current passed from stack to stack pushes the domain wall, repositioning the domain wall within the free layer. The position of the domain wall relative to the magnetic tunnel junction corresponds to a unique resistance value, and passing current from a stack to the magnetic tunnel junction reads the magnetic memory element's resistance. Thus, unique memory states may be achieved by moving the domain wall.

    Abstract translation: 公开了一种包括自由层，两个堆叠和磁性隧道结的多状态低电流切换磁存储元件（磁存储元件）。 堆叠和磁性隧道结设置在自由层的表面上，磁性隧道结位于堆叠之间。 堆叠在自由层内引导磁畴，产生自由层畴壁。 从堆栈传递到堆栈的电流推动域壁，重新定位自由层内的域壁。 畴壁相对于磁性隧道结的位置对应于唯一的电阻值，并且将电流从堆叠传递到磁性隧道结读取磁存储元件的电阻。 因此，可以通过移动域壁来实现唯一的记忆状态。

    METHOD FOR MANUFACTURING NON-VOLATILE MAGNETIC MEMORY
    53.
    发明申请
    METHOD FOR MANUFACTURING NON-VOLATILE MAGNETIC MEMORY 有权
    制造非易失性磁记忆的方法

    公开(公告)号：US20080293165A1

    公开(公告)日：2008-11-27

    申请号：US12040827

    申请日：2008-02-29

    Applicant: Rajiv Yadav RANJAN ,  Parviz KESHTBOD ,  Roger Klas MALMHALL

    Inventor： Rajiv Yadav RANJAN ,  Parviz KESHTBOD ,  Roger Klas MALMHALL

    IPC: H01L21/00

    CPC classification number: H01L43/12 ,  B82Y10/00 ,  B82Y25/00 ,  G11C11/16 ,  H01L27/228

    Abstract: In accordance with a method of the present invention, a method of manufacturing a magnetic random access memory (MRAM) cell and a corresponding structure thereof are disclosed to include a multi-stage manufacturing process. The multi-stage manufacturing process includes performing a front end on-line (FEOL) stage to manufacture logic and non-magnetic portions of the memory cell by forming an intermediate interlayer dielectric (ILD) layer, forming intermediate metal pillars embedded in the intermediate ILD layer, depositing a conductive metal cap on top of the intermediate ILD layer and the metal pillars, performing magnetic fabrication stage to make a magnetic material portion of the memory cell being manufactured, and performing back end on-line (BEOL) stage to make metal and contacts of the memory cell being manufactured.

    Abstract translation: 根据本发明的方法，公开了一种制造磁随机存取存储器（MRAM）单元及其相应结构的方法，以包括多级制造工艺。 多级制造过程包括通过形成中间层间电介质（ILD）层来形成前端在线（FEOL）级来制造存储单元的逻辑和非磁性部分，形成嵌入在中间ILD中的中间金属柱 层，在中间ILD层和金属柱的顶部上沉积导电金属帽，进行磁性制造阶段以制造存储单元的磁性材料部分，并执行后端在线（BEOL）阶段以制造金属 和正在制造的存储单元的触点。

    Non-Volatile Magnetic Memory with Low Switching Current and High Thermal Stability
    54.
    发明申请
    Non-Volatile Magnetic Memory with Low Switching Current and High Thermal Stability 有权
    具有低开关电流和高热稳定性的非易失性磁存储器

    公开(公告)号：US20080191251A1

    公开(公告)日：2008-08-14

    申请号：US11739648

    申请日：2007-04-24

    Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod

    Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod

    IPC: G11C11/22 ,  H01L43/12

    CPC classification number: H01L43/10 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1675 ,  H01L27/228

    Abstract: One embodiment of the present invention includes a an embodiment of the present invention includes a non-volatile current-switching magnetic memory element including a bottom electrode; a pinning layer formed on top of the bottom electrode; a fixed layer formed on top of the pinning layer; a tunnel layer formed on top of the pinning layer; a first free layer formed on top of the tunnel layer; a granular film layer formed on top of the free layer; a second free layer formed on top of the granular film layer; a cap layer formed on top of the second layer; and a top electrode formed on top of the cap layer.

    Abstract translation: 本发明的一个实施例包括本发明的一个实施例，其包括一个包括底部电极的非易失性电流切换磁存储元件; 形成在底部电极顶部的钉扎层; 形成在钉扎层顶部的固定层; 形成在钉扎层之上的隧道层; 形成在隧道层顶部的第一自由层; 形成在自由层顶部的粒状膜层; 形成在所述粒状膜层顶部的第二自由层; 盖层，形成在第二层的顶部; 以及形成在盖层顶部上的顶部电极。

    Redeposition control in MRAM fabrication process
    57.
    发明授权
    Redeposition control in MRAM fabrication process 有权
    MRAM制造工艺中的再沉积控制

    公开(公告)号：US08883520B2

    公开(公告)日：2014-11-11

    申请号：US13530381

    申请日：2012-06-22

    Applicant: Kimihiro Satoh ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Parviz Keshtbod ,  Yiming Huai ,  Jing Zhang

    Inventor： Kimihiro Satoh ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Parviz Keshtbod ,  Yiming Huai ,  Jing Zhang

    IPC: H01L21/00

    CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/12

    Abstract: Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode.

    Abstract translation: 描述了方法和结构以在柱蚀刻期间减少存储器单元（例如MTJ电池）中的金属沉积材料。 一个实施例在位于晶片上暴露的金属表面的电介质层中的着陆焊盘的顶部上形成金属螺柱。 另一个实施例分别对MTJ和底部电极进行图案化。 底部电极掩模然后覆盖底部电极下面的金属。 另一实施例将柱蚀刻工艺分为两个阶段。 第一阶段蚀刻到较低的磁性层，然后阻挡层的侧壁被电介质材料覆盖，然后将其垂直蚀刻。 蚀刻的第二阶段然后对剩余的层进行图案化。 另一个实施例使用顶部电极上方的硬掩模来蚀刻MTJ柱直到靠近底部电极的端点，沉积电介质，然后垂直蚀刻剩余的底部电极。

    Multi-port magnetic random access memory (MRAM)
    60.
    发明授权
    Multi-port magnetic random access memory (MRAM) 有权
    多端口磁随机存取存储器（MRAM）

    公开(公告)号：US08670264B1

    公开(公告)日：2014-03-11

    申请号：US13585774

    申请日：2012-08-14

    Applicant: Ebrahim Abedifard ,  Parviz Keshtbod

    Inventor： Ebrahim Abedifard ,  Parviz Keshtbod

    IPC: G11C11/21

    CPC classification number: G11C11/1673 ,  G11C8/16 ,  G11C11/16 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675

    Abstract: A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor is coupled to the resistive element and to a second source line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line. The memory array further has other resistive elements that are each coupled to the bit line. The resistive element is written to while one or more of the other resistive elements are being read.

    Abstract translation: 存储器阵列被组织成电阻元件的行和列，并且被公开为包括要读取或要写入的电阻元件。 此外，第一存取晶体管耦合到电阻元件和第一源极线，第二存取晶体管耦合到电阻元件和第二源极线，电阻元件在一端被耦合到第一和第二存取 晶体管和位线的相对端。 存储器阵列还具有各自耦合到位线的其它电阻元件。 在读取其中一个或多个其它电阻元件的同时写入电阻元件。

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