公开(公告)号：US06794756B2

公开(公告)日：2004-09-21

申请号：US10153011

申请日：2002-05-21

申请人： Weidan Li ,  Wilbur G. Catabay ,  Wei-Jen Hsia

发明人： Weidan Li ,  Wilbur G. Catabay ,  Wei-Jen Hsia

IPC分类号： H01L2348

CPC分类号： H01L21/76802 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76837

摘要： A capping layer of an insulator such as silicon oxynitride is formed over horizontally closely spaced apart metal lines on an oxide layer of an integrated circuit structure formed on a semiconductor substrate. Low k silicon oxide dielectric material which exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines is then deposited over and between the metal lines and over the silicon oxynitride caps on the metal lines. After the formation of such void-free low k silicon oxide dielectric material between the closely spaced apart metal lines and the silicon oxynitride caps thereon, the structure is planarized to bring the level of the low k silicon oxide dielectric material down to the level of the tops of the silicon oxynitride caps on the metal lines. A further layer of standard k silicon oxide dielectric material is then formed over the planarized void-free low k silicon oxide dielectric layer and the silicon oxynitride caps. Vias are then formed through the standard k silicon oxide dielectric layer and the silicon oxynitride caps down to the metal lines. Since the vias are not formed through the low k silicon oxide dielectric material, formation of the vias does not contribute to poisoning of the vias. However, the presence of the low k silicon oxide dielectric material between the horizontally closely spaced apart metal lines reduces the horizontal capacitance between such metal lines.

摘要翻译： 在形成在半导体衬底上的集成电路结构的氧化物层上的水平间隔开的金属线上形成有诸如氮氧化硅的绝缘体的覆盖层。 然后，在紧密间隔开的金属线之间的高纵横比区域中显示无空隙沉积性质的低k氧化硅电介质材料沉积在金属线之间并且在金属线上的氮氧化硅帽上方。 在这种无空隙的低k氧化硅电介质材料形成在紧密分开的金属线和其上的氧氮化硅帽之间形成之后，该结构被平坦化以使低k氧化硅电介质材料的电平降低到 金属线上的氧氮化硅盖的顶部。 然后在平坦化的无空隙低k氧化硅介电层和氮氧化硅盖上形成另一层标准的k氧化硅电介质材料。 然后通过标准的k氧化硅介电层形成通孔，并将氮氧化硅覆盖到金属线上。 由于通孔不通过低k氧化硅电介质材料形成，所以通孔的形成不会导致通孔的中毒。 然而，在水平间隔开的金属线之间的低k氧化硅电介质材料的存在降低了这些金属线之间的水平电容。

公开(公告)号：US06790784B2

公开(公告)日：2004-09-14

申请号：US10422270

申请日：2003-04-24

申请人： Wilbur G. Catabay ,  Wei-Jen Hsia

发明人： Wilbur G. Catabay ,  Wei-Jen Hsia

IPC分类号： H01L21302

CPC分类号： H01L21/76829 ,  H01L21/31058 ,  H01L21/31138 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76825

摘要： A process for forming an integrated circuit structure comprises forming a layer of low k dielectric material over a previously formed integrated circuit structure, and treating the upper surface of the layer of low k dielectric material with a plasma to form a layer of densified dielectric material over the remainder of the underlying layer of low k dielectric material, forming a second layer of low k dielectric material over the layer of densified dielectric material, and treating this second layer of low k dielectric material to form a second layer of densified dielectric material over the second layer of low k dielectric material. The layer or layers of densified dielectric material formed from the low k dielectric material provide mechanical support and can then function as etch stop and mask layers for the formation of vias and/or trenches.

摘要翻译： 一种用于形成集成电路结构的工艺包括在先前形成的集成电路结构上形成低k电介质材料层，并用等离子体处理低k电介质材料层的上表面以形成一层致密的电介质材料， 低k介电材料的下层的剩余部分，在致密化介电材料层上形成第二层低k电介质材料层，并处理该第二层低k电介质材料以形成第二层致密电介质材料 第二层低k电介质材料。 由低k电介质材料形成的致密化介电材料的层或层提供机械支撑，并且然后可以用作用于形成通孔和/或沟槽的蚀刻停止层和掩​​模层。

公开(公告)号：US06767832B1

公开(公告)日：2004-07-27

申请号：US09844352

申请日：2001-04-27

申请人： Kiran Kumar ,  Zhihai Wang ,  Wilbur G. Catabay ,  Kai Zhang

发明人： Kiran Kumar ,  Zhihai Wang ,  Wilbur G. Catabay ,  Kai Zhang

IPC分类号： H01L21302

CPC分类号： H01L21/67207 ,  H01L21/67167 ,  H01L21/76802 ,  H01L21/76843

摘要： A method of processing a substrate, where the substrate is transferred from an ambient environment into a clean environment. The substrate is heated to at least a first temperature within the clean environment, and then maintained at no less than the first temperature within the clean environment. The substrate is selectively transferred within the clean environment to more than one processing chambers, and processed in the more than one processing chambers. The substrate is transferred from the clean environment into the ambient environment.

摘要翻译： 一种处理衬底的方法，其中衬底从周围环境转移到清洁环境中。 将衬底加热至清洁环境中的至少第一温度，然后在清洁环境内保持不低于第一温度。 衬底被选择性地在干净的环境中转移到多于一个的处理室，并在多于一个的处理室中进行处理。 衬底从干净的环境转移到周围的环境中。

公开(公告)号：US06756674B1

公开(公告)日：2004-06-29

申请号：US09426061

申请日：1999-10-22

申请人： Wilbur G. Catabay ,  Wei-Jen Hsia ,  Weidan Li ,  Joe W. Zhao

发明人： Wilbur G. Catabay ,  Wei-Jen Hsia ,  Weidan Li ,  Joe W. Zhao

IPC分类号： H01L2348

CPC分类号： H01L21/02126 ,  C23C16/402 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/3146 ,  H01L21/31612 ,  H01L21/76801 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure is disclosed wherein the capacitance between nearby conductive portions may be lowered using carbon-containing low k silicon oxide dielectric material, without contributing to the problem of via poisoning, by careful control of the carbon content of the dielectric material in two regions of the integrated circuit structure. The first region comprises the region between adjacent raised conductive lines formed over an underlying insulation layer, where undesirable capacitance may be formed horizontally between such adjacent conductive lines, while the second region comprises the region above the raised conductive lines where vias are normally formed extending upward from the raised conductive lines through the dielectric layer to an overlying layer of metal interconnects. In one embodiment, the carbon-containing low k silicon oxide dielectric material used in the first region between adjacent raised conductive lines has a high carbon content to provide maximum reduction of the dielectric constant of the dielectric material for maximum reduction in the horizontal capacitance developed between horizontally adjacent lines, while the carbon-containing low k silicon oxide dielectric material used in the second region above the raised conductive lines has a reduced carbon content to mitigate poisoning of vias formed through the dielectric material in this second region. In another embodiment both the first and second regions have the same or similar reduced carbon content in the carbon-containing low k silicon oxide dielectric material used in both of the respective first and second regions to thereby provide a carbon content sufficient to lower the undesirable capacitance formed horizontally between said adjacent raised conductive lines in said first region, but insufficient to cause via poisoning in vias formed in said second region.

公开(公告)号：US06734560B2

公开(公告)日：2004-05-11

申请号：US10238073

申请日：2002-09-09

申请人： Wilbur G. Catabay ,  Zhihai Wang

发明人： Wilbur G. Catabay ,  Zhihai Wang

IPC分类号： H01L2348

CPC分类号： H01L21/76846

摘要： An integrated circuit including an electrically conductive interconnect having a first barrier layer consisting essentially of a diamond film. A seed layer consisting essentially of copper is disposed adjacent the first barrier layer. A conductive layer consisting essentially of copper is disposed adjacent the seed layer.

摘要翻译： 一种集成电路，包括具有主要由金刚石膜组成的第一阻挡层的导电互连。 基本上由铜组成的种子层设置在第一阻挡层附近。 基本上由铜组成的导电层设置在种子层附近。

公开(公告)号：US06686272B1

公开(公告)日：2004-02-03

申请号：US10020084

申请日：2001-12-13

申请人： Sang-Yun Lee ,  Masaichi Eda ,  Hongqiang Lu ,  Wei-Jen Hsia ,  Wilbur G. Catabay ,  Hiroaki Takikawa ,  Yongbae Kim

发明人： Sang-Yun Lee ,  Masaichi Eda ,  Hongqiang Lu ,  Wei-Jen Hsia ,  Wilbur G. Catabay ,  Hiroaki Takikawa ,  Yongbae Kim

IPC分类号： H01L214763

CPC分类号： H01L21/02126 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/0276 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76835 ,  Y10S438/931 ,  Y10S438/952

摘要： The present invention is directed to a silicon carbide anti-reflective coating (ARC) and a silicon oxycarbide ARC. Another embodiment is directed to a silicon oxycarbide ARC that is treated with oxygen plasma. The invention includes method embodiments for forming silicon carbide layers and silicon oxycarbide layers as ARC's on a semiconductor substrate surface. Particularly, the methods include introducing methyl silane materials into a process chamber where they are ignited as plasma and deposited onto the substrate surface as silicon carbide. Another method includes introducing methyl silane precursor materials with an inert carrier gas into the process chamber with oxygen. These materials are ignited into a plasma, and silicon oxycarbide material is deposited onto the substrate. By regulating the oxygen flow rate, the optical properties of the silicon oxycarbide layer can be adjusted. In another embodiment, the silicon oxycarbide layer can be treated with oxygen plasma.

摘要翻译： 本发明涉及碳化硅抗反射涂层（ARC）和碳氧化硅ARC。 另一个实施方案涉及用氧等离子体处理的碳氧化硅ARC。 本发明包括在半导体衬底表面上形成碳化硅层和碳氧化硅层作为ARC的方法实施例。 特别地，所述方法包括将甲基硅烷材料引入处理室中，其中它们被等离子体点燃并作为碳化硅沉积在基板表面上。 另一种方法包括将具有惰性载气的甲基硅烷前体材料用氧气引入到处理室中。 将这些材料点燃到等离子体中，并将​​碳氧化硅材料沉积到基底上。 通过调节氧气流速，可以调节碳硅氧烷层的光学性能。 在另一个实施方案中，可以用氧等离子体处理碳氧化硅层。

公开(公告)号：US06528423B1

公开(公告)日：2003-03-04

申请号：US10002831

申请日：2001-10-26

申请人： Wilbur G. Catabay ,  Wei-Jen Hsia

发明人： Wilbur G. Catabay ,  Wei-Jen Hsia

IPC分类号： H01L2144

CPC分类号： H01L23/53238 ,  H01L21/31155 ,  H01L21/3146 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process for forming an integrated circuit structure characterized by formation of an improved barrier layer for protection against migration of copper from a copper-containing layer into low k dielectric material while mitigating undesired increase in dielectric constant and mitigating undesirable interference by materials in the barrier layer with subsequent photolithography. The steps of the process comprise: forming a copper-containing layer over an integrated circuit structure; forming a first barrier layer of silicon carbide over the copper-containing layer; exposing the first layer of silicon carbide to a plasma to insert, into the first barrier layer of silicon carbide, ions capable of enhancing the ability of the silicon carbide barrier layer to prevent diffusion of copper from the copper-containing layer through the silicon carbide barrier layer; and sequentially repeating the steps of forming a barrier layer and exposing the barrier layer to plasma for from 1 to 5 additional times to form a composite layer of silicon carbide layers, each (with the possible exception of the top layer) exposed to the plasma. Preferably, the plasma comprises ions of elements and compounds selected from the group consisting of O2, H2, CO2, He, Ar, NH3, N2, and combinations of such gases.

摘要翻译： 一种用于形成集成电路结构的方法，其特征在于形成改进的阻挡层，以防止铜从含铜层迁移到低k电介质材料中，同时减轻介电常数的不期望的增加并减轻阻挡层中材料的不期望的干扰 随后进行光刻。 该方法的步骤包括：在集成电路结构上形成含铜层; 在含铜层上形成碳化硅的第一阻挡层; 将第一层碳化硅暴露于等离子体以将碳化硅的第一阻挡层插入到能够增强碳化硅阻挡层以防止铜从含铜层扩散通过碳化硅阻挡层的能力的离子 层; 并顺序地重复形成阻挡层并且将阻挡层暴露于等离子体1至5次的步骤以形成暴露于等离子体的每个（除了顶层之外）的碳化硅层的复合层。 优选地，等离子体包括选自O 2，H 2，CO 2，He，Ar，NH 3，N 2以及这些气体的组合的元素和化合物的离子。

公开(公告)号：US06518193B1

公开(公告)日：2003-02-11

申请号：US09802424

申请日：2001-03-09

申请人： Kiran Kumar ,  Zhihai Wang ,  Rudy Rios ,  Wilbur G. Catabay ,  Richard D. Schinella

发明人： Kiran Kumar ,  Zhihai Wang ,  Rudy Rios ,  Wilbur G. Catabay ,  Richard D. Schinella

IPC分类号： H01L21302

CPC分类号： H01L21/67167 ,  C23C14/566 ,  C23C16/4401 ,  H01L21/67017 ,  H01L21/67201 ,  H01L21/76802 ,  H01L21/76843

摘要： An apparatus for performing contaminant sensitive processing on a substrate. A substrate load chamber receives the substrate from an ambient contaminant laden environment, and isolates the substrate from the ambient contaminant laden environment. The substrate load chamber further forms a first environment of intermediate cleanliness around the substrate. A substrate pass through chamber receives the substrate from the substrate load chamber, and isolates the substrate from the intermediate cleanliness of the first environment of the substrate load chamber. The substrate pass through chamber further forms a second environment of high cleanliness around the substrate. A substrate transfer chamber receives the substrate from the substrate pass through chamber, and isolates the substrate from the high cleanliness of the second environment of the substrate pass through chamber. The substrate transfer chamber maintains a third environment of high cleanliness around the substrate, and transfers the substrate into more than one substrate processing chambers, where the substrate is selectively transferred into and out of the more than one substrate processing chambers without leaving the high cleanliness of the third environment. The substrate transfer chamber also selectively passes the substrate to the substrate pass through chamber when the substrate pass through chamber has formed the high cleanliness of the second environment. The substrate pass through chamber also receives the substrate from the substrate transfer chamber, and selectively passes the substrate to the substrate load chamber when the substrate load chamber has formed the intermediate cleanliness of the first environment. The substrate load chamber receives the substrate from the substrate pass through chamber, and selectively passes the substrate out of the substrate load chamber and into the ambient contaminant laden environment when the substrate load chamber is not open to the substrate pass through chamber.

公开(公告)号：US06423628B1

公开(公告)日：2002-07-23

申请号：US09425552

申请日：1999-10-22

申请人： Weidan Li ,  Wilbur G. Catabay ,  Wei-Jen Hsia

发明人： Weidan Li ,  Wilbur G. Catabay ,  Wei-Jen Hsia

IPC分类号： H01L214763

CPC分类号： H01L21/76802 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76837

摘要： A capping layer of an insulator such as silicon oxynitride is formed over horizontally closely spaced apart metal lines on an oxide layer of an integrated circuit structure formed on a semiconductor substrate. Low k silicon oxide dielectric material which exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines is then deposited over and between the metal lines and over the silicon oxynitride caps on the metal lines. After the formation of such void-free low k silicon oxide dielectric material between the closely spaced apart metal lines and the silicon oxynitride caps thereon, the structure is planarized to bring the level of the low k silicon oxide dielectric material down to the level of the tops of the silicon oxynitride caps on the metal lines. A further layer of standard k silicon oxide dielectric material is then formed over the planarized void-free low k silicon oxide dielectric layer and the silicon oxynitride caps. Vias are then formed through the standard k silicon oxide dielectric layer and the silicon oxynitride caps down to the metal lines. Since the vias are not formed through the low k silicon oxide dielectric material, formation of the vias does not contribute to poisoning of the vias. However, the presence of the low k silicon oxide dielectric material between the horizontally closely spaced apart metal lines reduces the horizontal capacitance between such metal lines.

摘要翻译： 在形成在半导体衬底上的集成电路结构的氧化物层上的水平间隔开的金属线上形成有诸如氮氧化硅的绝缘体的覆盖层。 然后，在紧密间隔开的金属线之间的高纵横比区域中显示无空隙沉积性质的低k氧化硅电介质材料沉积在金属线之间并且在金属线上的氮氧化硅帽上方。 在这种无空隙的低k氧化硅电介质材料形成在紧密分开的金属线和其上的氧氮化硅帽之间形成之后，该结构被平坦化以使低k氧化硅电介质材料的电平降低到 金属线上的氧氮化硅盖的顶部。 然后在平坦化的无空隙低k氧化硅介电层和氮氧化硅盖上形成另一层标准的k氧化硅电介质材料。 然后通过标准的k氧化硅介电层形成通孔，并将氮氧化硅覆盖到金属线上。 由于通孔不通过低k氧化硅电介质材料形成，所以通孔的形成不会导致通孔的中毒。 然而，在水平间隔开的金属线之间的低k氧化硅电介质材料的存在降低了这些金属线之间的水平电容。

公开(公告)号：US06420277B1

公开(公告)日：2002-07-16

申请号：US09704635

申请日：2000-11-01

申请人： Wilbur G. Catabay ,  Wei-Jen Hsia ,  Hong Qiang

发明人： Wilbur G. Catabay ,  Wei-Jen Hsia ,  Hong Qiang

IPC分类号： H01L2131

CPC分类号： H01L21/02126 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31612 ,  H01L21/31633 ,  H01L21/76828 ,  H01L21/76829

摘要： A process is disclosed which inhibits cracking of the layer of low k silicon oxide dielectric material on an integrated circuit structure during subsequent processing of the layer of low k silicon oxide dielectric material. The process comprises: forming a layer of low k silicon oxide dielectric material on an integrated circuit structure on a semiconductor substrate, and forming over the layer of low k silicon oxide dielectric material a capping layer of dielectric material having: a dielectric constant not exceeding about 4, a thickness of at least about 300 nm, and a compressive stress of at least about 3×109 dynes/cm2. In a preferred embodiment, the capping layer comprises silicon oxide formed by reaction of silane and N2O in a PECVD process carried out within a pressure range of from about 600 milliTorr to about 1000 milliTorr; and a temperature range of from about 300° C. to about 400° C.; while maintaining a plasma at a power level ranging from about 250 watts to about 350 watts; a flow of silane equivalent to a flow of from about 35 sccm to about 45 sccm into a 10 liter reactor; and a flow of N2O equivalent to a flow of from about 3800 sccm to about 4200 sccm into the 10 liter reactor.

摘要翻译： 公开了一种在低k氧化硅介电材料层的后续处理期间抑制集成电路结构上的低k氧化硅介电材料层的破裂的方法。 该方法包括：在半导体衬底上的集成电路结构上形成低k氧化硅介电材料层，并在低k氧化硅电介质材料的层上形成介电材料的覆盖层，该覆盖层的介电常数不超过约 4，至少约300nm的厚度和至少约3×10 9达因/ cm 2的压缩应力。 在优选实施例中，封盖层包括通过在约600毫乇至约1000毫乇的压力范围内进行的PECVD工艺中硅烷和N 2 O反应形成的氧化硅; 温度范围为约300℃至约400℃; 同时将等离子体维持在从约250瓦至约350瓦特的功率水平; 相当于约35sccm至约45sccm的硅烷流入10升反应器中的硅烷流; 以及相当于流量为约3800sccm至约4200sccm的N2O流入10升反应器。