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    Low dielectric constant silicon oxide-based dielectric layer for integrated circuit structures having improved compatibility with via filler materials, and method of making same
    1.
    发明授权
    Low dielectric constant silicon oxide-based dielectric layer for integrated circuit structures having improved compatibility with via filler materials, and method of making same 有权

    公开(公告)号：US06756674B1

    公开(公告)日：2004-06-29

    申请号：US09426061

    申请日：1999-10-22

    申请人： Wilbur G. Catabay ,  Wei-Jen Hsia ,  Weidan Li ,  Joe W. Zhao

    发明人： Wilbur G. Catabay ,  Wei-Jen Hsia ,  Weidan Li ,  Joe W. Zhao

    IPC分类号： H01L2348

    CPC分类号： H01L21/02126 ,  C23C16/402 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/3146 ,  H01L21/31612 ,  H01L21/76801 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit structure is disclosed wherein the capacitance between nearby conductive portions may be lowered using carbon-containing low k silicon oxide dielectric material, without contributing to the problem of via poisoning, by careful control of the carbon content of the dielectric material in two regions of the integrated circuit structure. The first region comprises the region between adjacent raised conductive lines formed over an underlying insulation layer, where undesirable capacitance may be formed horizontally between such adjacent conductive lines, while the second region comprises the region above the raised conductive lines where vias are normally formed extending upward from the raised conductive lines through the dielectric layer to an overlying layer of metal interconnects. In one embodiment, the carbon-containing low k silicon oxide dielectric material used in the first region between adjacent raised conductive lines has a high carbon content to provide maximum reduction of the dielectric constant of the dielectric material for maximum reduction in the horizontal capacitance developed between horizontally adjacent lines, while the carbon-containing low k silicon oxide dielectric material used in the second region above the raised conductive lines has a reduced carbon content to mitigate poisoning of vias formed through the dielectric material in this second region. In another embodiment both the first and second regions have the same or similar reduced carbon content in the carbon-containing low k silicon oxide dielectric material used in both of the respective first and second regions to thereby provide a carbon content sufficient to lower the undesirable capacitance formed horizontally between said adjacent raised conductive lines in said first region, but insufficient to cause via poisoning in vias formed in said second region.

    Integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines
    2.
    发明授权
    Integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines 有权
    具有低介电常数材料并且在紧密间隔开的金属线上具有氧氮化硅盖的集成电路结构

    公开(公告)号：US06794756B2

    公开(公告)日：2004-09-21

    申请号：US10153011

    申请日：2002-05-21

    申请人： Weidan Li ,  Wilbur G. Catabay ,  Wei-Jen Hsia

    发明人： Weidan Li ,  Wilbur G. Catabay ,  Wei-Jen Hsia

    IPC分类号： H01L2348

    CPC分类号： H01L21/76802 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76837

    摘要： A capping layer of an insulator such as silicon oxynitride is formed over horizontally closely spaced apart metal lines on an oxide layer of an integrated circuit structure formed on a semiconductor substrate. Low k silicon oxide dielectric material which exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines is then deposited over and between the metal lines and over the silicon oxynitride caps on the metal lines. After the formation of such void-free low k silicon oxide dielectric material between the closely spaced apart metal lines and the silicon oxynitride caps thereon, the structure is planarized to bring the level of the low k silicon oxide dielectric material down to the level of the tops of the silicon oxynitride caps on the metal lines. A further layer of standard k silicon oxide dielectric material is then formed over the planarized void-free low k silicon oxide dielectric layer and the silicon oxynitride caps. Vias are then formed through the standard k silicon oxide dielectric layer and the silicon oxynitride caps down to the metal lines. Since the vias are not formed through the low k silicon oxide dielectric material, formation of the vias does not contribute to poisoning of the vias. However, the presence of the low k silicon oxide dielectric material between the horizontally closely spaced apart metal lines reduces the horizontal capacitance between such metal lines.

    摘要翻译： 在形成在半导体衬底上的集成电路结构的氧化物层上的水平间隔开的金属线上形成有诸如氮氧化硅的绝缘体的覆盖层。 然后，在紧密间隔开的金属线之间的高纵横比区域中显示无空隙沉积性质的低k氧化硅电介质材料沉积在金属线之间并且在金属线上的氮氧化硅帽上方。 在这种无空隙的低k氧化硅电介质材料形成在紧密分开的金属线和其上的氧氮化硅帽之间形成之后，该结构被平坦化以使低k氧化硅电介质材料的电平降低到 金属线上的氧氮化硅盖的顶部。 然后在平坦化的无空隙低k氧化硅介电层和氮氧化硅盖上形成另一层标准的k氧化硅电介质材料。 然后通过标准的k氧化硅介电层形成通孔，并将氮氧化硅覆盖到金属线上。 由于通孔不通过低k氧化硅电介质材料形成，所以通孔的形成不会导致通孔的中毒。 然而，在水平间隔开的金属线之间的低k氧化硅电介质材料的存在降低了这些金属线之间的水平电容。

    Method of forming integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines
    3.
    发明授权
    Method of forming integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines 有权
    形成具有低介电常数材料的集成电路结构并且在紧密间隔开的金属线上具有氧氮化硅盖的方法

    公开(公告)号：US06423628B1

    公开(公告)日：2002-07-23

    申请号：US09425552

    申请日：1999-10-22

    申请人： Weidan Li ,  Wilbur G. Catabay ,  Wei-Jen Hsia

    发明人： Weidan Li ,  Wilbur G. Catabay ,  Wei-Jen Hsia

    IPC分类号： H01L214763

    CPC分类号： H01L21/76802 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76837

    摘要： A capping layer of an insulator such as silicon oxynitride is formed over horizontally closely spaced apart metal lines on an oxide layer of an integrated circuit structure formed on a semiconductor substrate. Low k silicon oxide dielectric material which exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines is then deposited over and between the metal lines and over the silicon oxynitride caps on the metal lines. After the formation of such void-free low k silicon oxide dielectric material between the closely spaced apart metal lines and the silicon oxynitride caps thereon, the structure is planarized to bring the level of the low k silicon oxide dielectric material down to the level of the tops of the silicon oxynitride caps on the metal lines. A further layer of standard k silicon oxide dielectric material is then formed over the planarized void-free low k silicon oxide dielectric layer and the silicon oxynitride caps. Vias are then formed through the standard k silicon oxide dielectric layer and the silicon oxynitride caps down to the metal lines. Since the vias are not formed through the low k silicon oxide dielectric material, formation of the vias does not contribute to poisoning of the vias. However, the presence of the low k silicon oxide dielectric material between the horizontally closely spaced apart metal lines reduces the horizontal capacitance between such metal lines.

    摘要翻译： 在形成在半导体衬底上的集成电路结构的氧化物层上的水平间隔开的金属线上形成有诸如氮氧化硅的绝缘体的覆盖层。 然后，在紧密间隔开的金属线之间的高纵横比区域中显示无空隙沉积性质的低k氧化硅电介质材料沉积在金属线之间并且在金属线上的氮氧化硅帽上方。 在这种无空隙的低k氧化硅电介质材料形成在紧密分开的金属线和其上的氧氮化硅帽之间形成之后，该结构被平坦化以使低k氧化硅电介质材料的电平降低到 金属线上的氧氮化硅盖的顶部。 然后在平坦化的无空隙低k氧化硅介电层和氮氧化硅盖上形成另一层标准的k氧化硅电介质材料。 然后通过标准的k氧化硅介电层形成通孔，并将氮氧化硅覆盖到金属线上。 由于通孔不通过低k氧化硅电介质材料形成，所以通孔的形成不会导致通孔的中毒。 然而，在水平间隔开的金属线之间的低k氧化硅电介质材料的存在降低了这些金属线之间的水平电容。

    Low via resistance system
    4.
    发明授权
    Low via resistance system 有权
    低通电阻系统

    公开(公告)号：US06569751B1

    公开(公告)日：2003-05-27

    申请号：US09617550

    申请日：2000-07-17

    申请人： Prabhakar P. Tripathi ,  Zhihai Wang ,  Weidan Li

    发明人： Prabhakar P. Tripathi ,  Zhihai Wang ,  Weidan Li

    IPC分类号： H01L2128

    CPC分类号： H01L21/76846 ,  C23C14/025 ,  C23C14/0641 ,  C23C14/345 ,  H01L21/2855

    摘要： A method of forming a metallization interconnection system within a via. A first liner layer of titanium is deposited to a first thickness in the following manner. A substrate containing the via is placed within an ion metal plasma deposition chamber that contains a titanium target. The ion metal plasma deposition chamber is evacuated to a first base pressure. A first flow of argon is introduced to the ion metal plasma deposition chamber at a first deposition pressure. The substrate is biased to a first voltage. A plasma within the ion metal plasma deposition chamber is energized at a first power for a first length of time. A second liner layer of TixNy is deposited to a second thickness on top of the first liner layer of titanium in the following manner. A first flow of nitrogen and a second flow of argon are introduced to the ion metal plasma deposition chamber at a second deposition pressure. The substrate is biased to a second voltage. The plasma within the ion metal plasma deposition chamber is energized at a second power for a second length of time, after which the substrate is removed from the ion metal plasma deposition chamber. Finally, a third liner layer of titanium nitride is deposited in a second deposition chamber, and a plug of tungsten is deposited.

    摘要翻译： 在通孔内形成金属化互连系统的方法。 钛的第一衬里层以下列方式沉积到第一厚度。 将含有通孔的基板放置在含有钛靶的离子金属等离子体沉积室内。 离子金属等离子体沉积室被抽空到第一基础压力。 在第一沉积压力下将第一氩气流引入离子金属等离子体沉积室。 衬底被偏压到第一电压。 离子金属等离子体沉积室内的等离子体在第一时间内以第一功率通电。 TixNy的第二衬里层以下列方式沉积在钛的第一内衬层的顶部上的第二厚度上。 在第二沉积压力下，将第一氮气流和第二氩气流引入离子金属等离子体沉积室。 衬底被偏压到第二电压。 离子金属等离子体沉积室内的等离子体以第二功率被施加第二时间长度，之后从离子金属等离子体沉积室中除去衬底。 最后，在第二沉积室中沉积氮化钛的第三衬里层，并沉积钨塞。

    Optimized buffering for JTAG boundary scan nets
    5.
    发明授权
    Optimized buffering for JTAG boundary scan nets 失效
    用于JTAG边界扫描网络的优化缓冲

    公开(公告)号：US07000163B1

    公开(公告)日：2006-02-14

    申请号：US10082737

    申请日：2002-02-25

    申请人： Juergen Dirks ,  Juergen K. Lahner ,  Ludger F. Johanterwage ,  Benjamin Mbouombouo ,  Human Boluki ,  Weidan Li

    发明人： Juergen Dirks ,  Juergen K. Lahner ,  Ludger F. Johanterwage ,  Benjamin Mbouombouo ,  Human Boluki ,  Weidan Li

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318572 ,  G01R31/318541

    摘要： An apparatus comprising one or more groups of boundary scan cells, one or more group buffers, one or more repeater buffers and a controller. The group buffers may be coupled to each of the groups of boundary scan cells. The repeater buffers may be coupled in series with the group buffers. The controller may be coupled to the groups of boundary scan cells through the group buffers and the repeater buffers. The apparatus may be configured to buffer the groups of boundary scan cells to reflect an order of I/Os around the apparatus.

    摘要翻译： 一种包括一组或多组边界扫描单元，一个或多个组缓冲器，一个或多个中继器缓冲器和控制器的装置。 组缓冲器可以耦合到每个边界扫描单元组。 中继器缓冲器可以与组缓冲器串联耦合。 控制器可以通过组缓冲器和中继器缓冲器耦合到边界扫描单元组。 该装置可以被配置为缓冲边界扫描单元组以反映设备周围的I / O的顺序。

    Low leakage PMOS on-chip decoupling capacitor cells compatible with standard CMOS cells
    6.
    发明授权
    Low leakage PMOS on-chip decoupling capacitor cells compatible with standard CMOS cells 有权
    低泄漏PMOS片上去耦电容电池与标准CMOS电池兼容

    公开(公告)号：US06608365B1

    公开(公告)日：2003-08-19

    申请号：US10163120

    申请日：2002-06-04

    申请人： Weidan Li ,  Benjamin Mbouombouo ,  Johann Leyrer

    发明人： Weidan Li ,  Benjamin Mbouombouo ,  Johann Leyrer

    IPC分类号： H01L2900

    CPC分类号： H01L27/0811 ,  H01L29/94

    摘要： An on-chip decoupling capacitor cell is disclosed that is compatible with standard CMOS cells. A cell boundary defining the area of the cell includes a first transistor area and a second transistor area. A PMOS transistor having an n-well is formed within the first transistor area. The on-chip decoupling capacitor cell further includes an n-well extension that extends the n-well into the second transistor area, thereby providing a decoupling capacitor cell having reduced leakage compared to a CMOS capacitor cell, and increased capacitance per unit area compare with a traditional PMOS capacitor cell.

    摘要翻译： 公开了与标准CMOS电池兼容的片上去耦电容器单元。 限定单元的区域的单元边界包括第一晶体管区域和第二晶体管区域。 具有n阱的PMOS晶体管形成在第一晶体管区域内。 片上去耦电容器单元还包括将n阱扩展到第二晶体管区域中的n阱延伸，从而提供与CMOS电容器单元相比具有减小的泄漏的去耦电容器单元，并且与单位面积相比增加了每单位面积的电容 一个传统的PMOS电容单元。

    On-chip automatic process variation, supply voltage variation, and temperature deviation (PVT) compensation method
    8.
    发明授权
    On-chip automatic process variation, supply voltage variation, and temperature deviation (PVT) compensation method 有权
    片上自动过程变化，电源电压变化和温度偏差（PVT）补偿方法

    公开(公告)号：US07321254B2

    公开(公告)日：2008-01-22

    申请号：US11004415

    申请日：2004-12-03

    申请人： Weidan Li ,  Benjamin Mbouombouo ,  Johann Leyrer

    发明人： Weidan Li ,  Benjamin Mbouombouo ,  Johann Leyrer

    IPC分类号： H03K3/01

    CPC分类号： H03K3/0315

    摘要： An on-chip substrate voltage controller which includes a plurality of chains of interconnected loaded ring oscillators connected to a multiplexer, where the multiplexer is configured to average the outputs from all the chains of interconnected loaded ring oscillators. An output of the multiplexer is connected to a comparator, such as a phase detector. The comparator also receives an output from a PLL, and is configured to compare the output of the multiplexer to the output of the PLL. An output of the comparator is connected to the controllable voltage regulator. The controllable voltage regulator receives a voltage in as well as the output of the comparator, and applies a substrate bias depending on what is received from the comparator.

    摘要翻译： 片上基板电压控制器，其包括连接到多路复用器的多个互连的加载环形振荡器的链，其中多路复用器被配置为平均来自互连加载的环形振荡器的所有链的输出。 多路复用器的输出端连接到诸如相位检测器的比较器。 比较器还接收来自PLL的输出，并且被配置为将多路复用器的输出与PLL的输出进行比较。 比较器的输出端连接到可控电压调节器。 可控电压调节器接收比较器的电压以及比较器的输出，并根据从比较器接收的内容施加衬底偏置。

    Method of optimizing critical path delay in an integrated circuit design
    9.
    发明授权
    Method of optimizing critical path delay in an integrated circuit design 有权
    在集成电路设计中优化关键路径延迟的方法

    公开(公告)号：US07181712B2

    公开(公告)日：2007-02-20

    申请号：US10975981

    申请日：2004-10-27

    申请人： Benjamin Mbouombouo ,  Weidan Li ,  Dana Ahrens

    发明人： Benjamin Mbouombouo ,  Weidan Li ,  Dana Ahrens

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5031 ,  G06F17/5036

    摘要： A method and computer program product for optimizing critical path delay in an integrated circuit design include steps of: (a) receiving as input an integrated circuit design; (b) performing a timing/crosstalk analysis to identify each timing critical net in the integrated circuit design; (c) selecting an optimum interconnect configuration for minimizing path delay in each timing critical net; (e) performing a detailed routing that includes the selected optimum interconnect configuration for each timing critical net; and (f) generating as output the detailed routing.

    摘要翻译： 一种用于优化集成电路设计中的关键路径延迟的方法和计算机程序产品包括以下步骤：（a）作为输入接收集成电路设计; （b）执行定时/串扰分析以识别集成电路设计中的每个时序关键网; （c）选择最佳互连配置以最小化每个时序关键网络中的路径延迟; （e）执行详细路由，其包括针对每个定时关键网络的所选择的最佳互连配置; 和（f）生成详细路由的输出。

    On-chip automatic process variation, supply voltage variation, and temperature deviation (PVT) compensation method
    10.
    发明申请
    On-chip automatic process variation, supply voltage variation, and temperature deviation (PVT) compensation method 有权
    片上自动过程变化，电源电压变化和温度偏差（PVT）补偿方法

    公开(公告)号：US20060119420A1

    公开(公告)日：2006-06-08

    申请号：US11004415

    申请日：2004-12-03

    申请人： Weidan Li ,  Benjamin Mbouombouo ,  Johann Leyrer

    发明人： Weidan Li ,  Benjamin Mbouombouo ,  Johann Leyrer

    IPC分类号： G05F1/10

    CPC分类号： H03K3/0315

    摘要： An on-chip substrate voltage controller which includes a plurality of chains of interconnected loaded ring oscillators connected to a multiplexer, where the multiplexer is configured to average the outputs from all the chains of interconnected loaded ring oscillators. An output of the multiplexer is connected to a comparator, such as a phase detector. The comparator also receives an output from a PLL, and is configured to compare the output of the multiplexer to the output of the PLL. An output of the comparator is connected to the controllable voltage regulator. The controllable voltage regulator receives a voltage in as well as the output of the comparator, and applies a substrate bias depending on what is received from the comparator.

    摘要翻译： 片上基板电压控制器，其包括连接到多路复用器的多个互连的加载环形振荡器的链，其中多路复用器被配置为平均来自互连加载的环形振荡器的所有链的输出。 多路复用器的输出端连接到诸如相位检测器的比较器。 比较器还接收来自PLL的输出，并且被配置为将多路复用器的输出与PLL的输出进行比较。 比较器的输出端连接到可控电压调节器。 可控电压调节器接收比较器的电压以及比较器的输出，并根据从比较器接收的内容施加衬底偏置。