公开(公告)号：US08691645B2

公开(公告)日：2014-04-08

申请号：US13572487

申请日：2012-08-10

申请人： Yukio Hayakawa ,  Hiroyuki Nansei

发明人： Yukio Hayakawa ,  Hiroyuki Nansei

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/76

CPC分类号： H01L27/11517 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L23/5283 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66757 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density, and a method of manufacturing such a semiconductor device. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines on the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed.

摘要翻译： 本发明提供一种半导体器件，其位线之间的距离较短，并且容易实现更高的存储容量和密度，以及制造这种半导体器件的方法。 半导体器件包括：形成在衬底上的第一位线; 绝缘层，设置在所述基板上的所述第一位线之间，并且具有比所述第一位线更高的上表面; 沟道层，其设置在绝缘层的两个侧面上，并且耦合到相应的第一位线; 并且从形成有绝缘层的侧面向沟道层的相对侧面设置电荷存储层。

公开(公告)号：US08481990B2

公开(公告)日：2013-07-09

申请号：US13375027

申请日：2011-03-07

申请人： Yoshio Kawashima ,  Takumi Mikawa ,  Yukio Hayakawa

发明人： Yoshio Kawashima ,  Takumi Mikawa ,  Yukio Hayakawa

IPC分类号： H01L47/00

CPC分类号： H01L45/146 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

摘要： A variable resistance nonvolatile memory element capable of suppressing a variation in resistance values is provided. A nonvolatile memory element according to the present invention includes: a silicon substrate (11); a lower electrode layer (102) formed on the silicon substrate (11); a variable resistance layer formed on the lower electrode layer (102); an upper electrode layer (104) formed on the variable resistance layer; a second interlayer insulating layer (19) formed to directly cover at least side surfaces of the lower electrode layer (102) and the variable resistance layer; a stress buffering region layer (105) for buffering a stress on the upper electrode layer (104), the stress buffering region layer being formed to directly cover at least an upper surface and side surfaces of the upper electrode layer (104) and comprising a material having a stress smaller than a stress of an insulating layer used as the second interlayer insulating layer (19); a second contact (16) extending to the upper electrode layer (104); and a wiring pattern (18) connected to the second contact (16).

摘要翻译： 提供了能够抑制电阻值变化的可变电阻非易失性存储元件。 根据本发明的非易失性存储元件包括：硅衬底（11）; 形成在所述硅衬底（11）上的下电极层（102）; 形成在所述下电极层（102）上的可变电阻层; 形成在所述可变电阻层上的上电极层（104） 形成为直接覆盖下电极层（102）和可变电阻层的至少侧面的第二层间绝缘层（19） 用于缓冲上电极层（104）上的应力的应力缓冲区层（105），所述应力缓冲区层形成为直接覆盖上电极层（104）的上表面和侧表面，并包括 具有小于用作第二层间绝缘层（19）的绝缘层的应力的应力的材料; 延伸到上电极层（104）的第二触点（16）; 以及连接到第二触点（16）的布线图案（18）。

公开(公告)号：US20130128654A1

公开(公告)日：2013-05-23

申请号：US13814557

申请日：2012-06-07

申请人： Shinichi Yoneda ,  Yukio Hayakawa ,  Kiyotaka Tsuji

发明人： Shinichi Yoneda ,  Yukio Hayakawa ,  Kiyotaka Tsuji

IPC分类号： G11C13/00 ,  H01L45/00

CPC分类号： G11C13/0033 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/72 ,  H01L27/2409 ,  H01L45/00 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146

摘要： A nonvolatile memory element includes a current steering element which bidirectionally rectifies current in response to applied voltage and a variable resistance element connected in series with the current steering element. The current steering element includes an MSM diode and an MSM diode which are connected in series and each of which bidirectionally rectifies current in response to applied voltage. The MSM diode and the MSM diode include a lower electrode, a first current steering layer, a first metal layer, a second current steering layer, and an upper electrode which are stacked in this order. The current steering element has a breakdown current which is larger than an initial breakdown current which flows in the variable resistance element at the time of initial breakdown.

摘要翻译： 非易失性存储元件包括响应于所施加的电压双向整流电流的电流转向元件和与当前转向元件串联连接的可变电阻元件。 电流导向元件包括串联连接的MSM二极管和MSM二极管，并且其中的每一个响应于施加的电压双向整流电流。 MSM二极管和MSM二极管包括依次层叠的下电极，第一电流控制层，第一金属层，第二电流控制层和上电极。 当前的转向元件具有大于初始击穿时在可变电阻元件中流动的初始击穿电流的击穿电流。

公开(公告)号：US20120199805A1

公开(公告)日：2012-08-09

申请号：US13501228

申请日：2011-08-11

申请人： Haruyuki Sorada ,  Takeki Ninomiya ,  Takumi Mikawa ,  Yukio Hayakawa

发明人： Haruyuki Sorada ,  Takeki Ninomiya ,  Takumi Mikawa ,  Yukio Hayakawa

IPC分类号： H01L47/00 ,  H01L21/02

CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1675

摘要： Provided are a nonvolatile memory device which can suppress non-uniformity in initial breakdown voltages among nonvolatile memory elements and prevent reduction of yield, and a manufacturing method thereof. The nonvolatile memory device includes a nonvolatile memory element (108) having a stacked-layer structure in which a resistance variable layer (106) is parallel to a main surface of a substrate (117) and is planarized, and a plug (103) electrically connected to either a first electrode (105) or a second electrode (107), and an area of an end surface of a plug (103) at which the plug (103) and the nonvolatile memory element (108) are connected together, the end surface being parallel to the main surface of the substrate (117), is greater than a cross-sectional area of a cross-section of a first transition metal oxide layer (115) which is an electrically-conductive region, the cross-section being parallel to the main surface of the substrate (117).

摘要翻译： 提供一种能够抑制非易失性存储元件之间的初始击穿电压的不均匀性并且防止产量降低的非易失性存储器件及其制造方法。 非易失性存储器件包括具有堆叠层结构的非易失性存储元件（108），其中电阻变化层（106）平行于衬底（117）的主表面并被平坦化;以及电极（103） 连接到第一电极（105）或第二电极（107），以及插头（103）的端面（103）的与插头（103）和非易失性存储元件（108）连接在一起的区域， 平行于基板（117）的主表面的端面大于作为导电区域的第一过渡金属氧化物层（115）的截面的横截面积，横截面 平行于基板（117）的主表面。

公开(公告)号：US20120112153A1

公开(公告)日：2012-05-10

申请号：US13380159

申请日：2011-07-13

申请人： Takeki Ninomiya ,  Satoru Fujii ,  Yukio Hayakawa ,  Takumi Mikawa

发明人： Takeki Ninomiya ,  Satoru Fujii ,  Yukio Hayakawa ,  Takumi Mikawa

IPC分类号： H01L45/00

CPC分类号： H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

摘要： Provided is a nonvolatile memory device which requires a lower initializing voltage such that the nonvolatile memory device can be operated at a low voltage. The nonvolatile memory device (10) includes: a first electrode layer (105) formed above a semiconductor substrate (100); a first oxygen-deficient tantalum oxide layer (106x) formed on the first electrode layer (105) and having a composition represented by TaOx where 0.8≦x≦1.9; a second oxygen-deficient tantalum oxide layer (106y) formed on the first oxygen-deficient tantalum oxide layer (106x) and having a composition represented by TaOy where 2.1≦y; and a second electrode layer (107) formed on the second tantalum oxide layer (106y). The second tantalum oxide layer (106y) has a pillar structure including a plurality of pillars.

摘要翻译： 提供了一种非易失性存储器件，其需要较低的初始化电压，使得非易失性存储器件可以在低电压下操作。 非易失性存储器件（10）包括：形成在半导体衬底（100）上方的第一电极层（105）; 形成在第一电极层（105）上并具有由TaOx表示的组成的第一缺氧钽氧化物层（106x），其中0.8＆lt; 1; x＆nlE; 1.9; 在第一缺氧钽氧化物层（106x）上形成的第二氧缺陷氧化钽层（106y），其具有由TaOy表示的组成，其中2.1＆amp; 和形成在第二钽氧化物层（106y）上的第二电极层（107）。 第二钽氧化物层（106y）具有包括多个柱的柱结构。

公开(公告)号：US08143661B2

公开(公告)日：2012-03-27

申请号：US11539984

申请日：2006-10-10

申请人： Shenqing Fang ,  Rinji Sugino ,  Jayendra Bhakta ,  Takashi Orimoto ,  Hiroyuki Nansei ,  Yukio Hayakawa ,  Takayuki Maruyama ,  Hidehiko Shiraiwa ,  Kuo-Tung Chang ,  Lei Xue ,  Meng Ding ,  Amol Ramesh Joshi ,  YouSeok Suh ,  Harpreet Sachar

发明人： Shenqing Fang ,  Rinji Sugino ,  Jayendra Bhakta ,  Takashi Orimoto ,  Hiroyuki Nansei ,  Yukio Hayakawa ,  Takayuki Maruyama ,  Hidehiko Shiraiwa ,  Kuo-Tung Chang ,  Lei Xue ,  Meng Ding ,  Amol Ramesh Joshi ,  YouSeok Suh ,  Harpreet Sachar

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11568

摘要： A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.

摘要翻译： 提供一种存储单元系统，包括半导体衬底上的第一绝缘体层，第一绝缘体层上的电荷陷阱层和电荷陷阱层包括具有生长特性的第二绝缘体层的槽。

公开(公告)号：US20120068148A1

公开(公告)日：2012-03-22

申请号：US13375027

申请日：2011-03-07

申请人： Yoshio Kawashima ,  Takumi Mikawa ,  Yukio Hayakawa

发明人： Yoshio Kawashima ,  Takumi Mikawa ,  Yukio Hayakawa

IPC分类号： H01L47/00 ,  H01L21/02

CPC分类号： H01L45/146 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

摘要： A variable resistance nonvolatile memory element capable of suppressing a variation in resistance values is provided. A nonvolatile memory element according to the present invention includes: a silicon substrate (11); a lower electrode layer (102) formed on the silicon substrate (11); a variable resistance layer formed on the lower electrode layer (102); an upper electrode layer (104) formed on the variable resistance layer; a second interlayer insulating layer (19) formed to directly cover at least side surfaces of the lower electrode layer (102) and the variable resistance layer; a stress buffering region layer (105) for buffering a stress on the upper electrode layer (104), the stress buffering region layer being formed to directly cover at least an upper surface and side surfaces of the upper electrode layer (104) and comprising a material having a stress smaller than a stress of an insulating layer used as the second interlayer insulating layer (19); a second contact (16) extending to the upper electrode layer (104); and a wiring pattern (18) connected to the second contact (16).

摘要翻译： 提供了能够抑制电阻值变化的可变电阻非易失性存储元件。 根据本发明的非易失性存储元件包括：硅衬底（11）; 形成在所述硅基板（11）上的下电极层（102）。 形成在所述下电极层（102）上的可变电阻层; 形成在所述可变电阻层上的上电极层（104） 形成为直接覆盖下电极层（102）和可变电阻层的至少侧面的第二层间绝缘层（19） 用于缓冲上电极层（104）上的应力的应力缓冲区层（105），所述应力缓冲区层形成为直接覆盖上电极层（104）的上表面和侧表面，并包括 具有小于用作第二层间绝缘层（19）的绝缘层的应力的应力的材料; 延伸到上电极层（104）的第二触点（16）; 以及连接到第二触点（16）的布线图案（18）。

公开(公告)号：US20110116323A1

公开(公告)日：2011-05-19

申请号：US13012664

申请日：2011-01-24

申请人： Yukio HAYAKAWA

发明人： Yukio HAYAKAWA

IPC分类号： G11C11/34 ,  H01L21/336

CPC分类号： H01L27/11568 ,  G11C5/06 ,  G11C16/10 ,  H01L21/84 ,  H01L27/115 ,  H01L27/1203

摘要： The present invention provides a system comprising a semiconductor device, a method of controlling the semiconductor device in the system, and a method of manufacturing the semiconductor device in the system. The semiconductor device includes: a semiconductor region located in a semiconductor layer formed on an isolating layer; an ONO film on the semiconductor region; bit lines on either side of the semiconductor region, which are located in the semiconductor layer, and are in contact with the isolating layer; a device isolating region on two different sides of the semiconductor region from the sides on which the bit lines are located, the device isolating region being in contact with the isolating layer; and a first voltage applying unit that is coupled to the semiconductor region. In this semiconductor device, the semiconductor region is surrounded by the bit lines and the device isolating region, and is electrically isolated from other semiconductor regions.

摘要翻译： 本发明提供了一种包括半导体器件，系统中的半导体器件的控制方法以及系统中的半导体器件的制造方法的系统。 半导体器件包括：位于形成在隔离层上的半导体层中的半导体区域; 半导体区域上的ONO膜; 位于半导体层中的半导体区域的两侧的位线与隔离层接触; 所述器件隔离区域与所述隔离层接触的所述半导体区域的与所述位线相对的两侧的两个不同侧上的器件隔离区域; 以及耦合到所述半导体区域的第一电压施加单元。 在该半导体器件中，半导体区域被位线和器件隔离区域包围，并且与其他半导体区域电隔离。

公开(公告)号：US07902590B2

公开(公告)日：2011-03-08

申请号：US12004919

申请日：2007-12-21

申请人： Yukio Hayakawa

发明人： Yukio Hayakawa

IPC分类号： H01L21/8247

CPC分类号： H01L27/11568 ,  G11C5/06 ,  G11C16/10 ,  H01L21/84 ,  H01L27/115 ,  H01L27/1203

摘要： The present invention provides a system comprising a semiconductor device, a method of controlling the semiconductor device in the system, and a method of manufacturing the semiconductor device in the system. The semiconductor device includes: a semiconductor region located in a semiconductor layer formed on an isolating layer; an ONO film on the semiconductor region; bit lines on either side of the semiconductor region, which are located in the semiconductor layer, and are in contact with the isolating layer; a device isolating region on two different sides of the semiconductor region from the sides on which the bit lines are located, the device isolating region being in contact with the isolating layer; and a first voltage applying unit that is coupled to the semiconductor region. In this semiconductor device, the semiconductor region is surrounded by the bit lines and the device isolating region, and is electrically isolated from other semiconductor regions.

摘要翻译： 本发明提供了一种包括半导体器件，系统中的半导体器件的控制方法以及系统中的半导体器件的制造方法的系统。 半导体器件包括：位于形成在隔离层上的半导体层中的半导体区域; 半导体区域上的ONO膜; 位于半导体层中的半导体区域的两侧的位线与隔离层接触; 所述器件隔离区域与所述隔离层接触的所述半导体区域的与所述位线相对的两侧的两个不同侧上的器件隔离区域; 以及耦合到所述半导体区域的第一电压施加单元。 在该半导体器件中，半导体区域被位线和器件隔离区域包围，并且与其他半导体区域电隔离。

公开(公告)号：US20080166853A1

公开(公告)日：2008-07-10

申请号：US11963415

申请日：2007-12-21

申请人： Fumihiko INOUE ,  Yukio HAYAKAWA

发明人： Fumihiko INOUE ,  Yukio HAYAKAWA

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/3086

摘要： A method of manufacturing a semiconductor device includes forming a silicon nitride film having an opening portion on a semiconductor substrate, forming a silicon oxide film on the silicon nitride film and on a side face of the opening portion, performing an etching treatment to the silicon oxide film so that a sidewall is formed on the side face of the opening portion, forming a trench on the semiconductor substrate with use of the sidewall and the silicon nitride film as a mask, and forming an insulating layer in the trench. The step of forming the silicon oxide film includes oxidizing the silicon nitride film with a plasma oxidation method or a radical oxidation method.

摘要翻译： 一种制造半导体器件的方法包括在半导体衬底上形成具有开口部分的氮化硅膜，在氮化硅膜上和开口部分的侧面上形成氧化硅膜，对氧化硅进行蚀刻处理 膜，使得在开口部分的侧面上形成侧壁，利用侧壁和氮化硅膜作为掩模在半导体衬底上形成沟槽，并在沟槽中形成绝缘层。 形成氧化硅膜的步骤包括用等离子体氧化法或自由基氧化法氧化氮化硅膜。