-
公开(公告)号：US20140317358A1
公开(公告)日：2014-10-23
申请号：US13864670
申请日：2013-04-17
Applicant: APPLE INC.
Inventor： Stephan G. Meier , Gerard R. Williams, III
IPC: G06F12/08
CPC classification number: G06F12/0833 , G06F12/0804 , G06F12/0806 , G06F12/0815 , G06F12/0817 , G06F12/084 , G06F12/1027
Abstract: A system may include a command queue controller coupled to a number of clusters of cores, where each cluster includes a cache shared amongst the cores. An originating core of one of the clusters may detect a global maintenance command and send the global maintenance command to the command queue controller. The command queue controller may broadcast the global maintenance command to the clusters including the originating core's cluster. Each of the cores of the clusters may execute the global maintenance command. Each cluster may send an acknowledgement to the command queue controller upon completed execution of the global maintenance command by each core of the cluster. The command queue controller may also send, upon receiving an acknowledgement from each cluster, a final acknowledgement to the originating core's cluster.
Abstract translation: 系统可以包括耦合到多个核心集群的命令队列控制器，其中每个集群包括在核心之间共享的高速缓存。 其中一个集群的发起核心可以检测全局维护命令，并将全局维护命令发送到命令队列控制器。 命令队列控制器可以将全局维护命令广播到包括源核心集群在内的集群。 集群的每个核心都可以执行全局维护命令。 每个集群可以在集群的每个核心完成执行全局维护命令之后向命令队列控制器发送确认。 命令队列控制器还可以在收到来自每个集群的确认后，发送对发起核心集群的最终确认。
-
公开(公告)号：US20140215182A1
公开(公告)日：2014-07-31
申请号：US13750013
申请日：2013-01-25
Applicant: APPLE INC.
Inventor： Josh P. de Cesare , Gerard R. Williams, III , Michael J. Smith , Wei-Han Lien
IPC: G06F9/30
CPC classification number: G06F9/322 , G06F9/30076
Abstract: In an embodiment, an integrated circuit includes at least one processor. The processor may include a reset vector base address register configured to store a reset vector address for the processor. Responsive to a reset, the processor may be configured to capture a reset vector address on an input, updating the reset vector base address register. Upon release from reset, the processor may initiate instruction execution at the reset vector address. The integrated circuit may further include a logic circuit that is coupled to provide the reset vector address. The logic circuit may include a register that is programmable with the reset vector address. More particularly, in an embodiment, the register may be programmable via a write operation issued by the processor (e.g. a memory-mapped write operation). Accordingly, the reset vector address may be programmable in the integrated circuit, and may be changed from time to time.
Abstract translation: 在一个实施例中，集成电路包括至少一个处理器。 处理器可以包括被配置为存储处理器的复位向量地址的复位向量基地址寄存器。 响应于复位，处理器可以被配置为捕获输入上的复位向量地址，更新复位向量基地址寄存器。 当复位释放时，处理器可以在复位向量地址处启动指令执行。 集成电路还可以包括耦合以提供复位向量地址的逻辑电路。 逻辑电路可以包括可用复位向量地址编程的寄存器。 更具体地，在一个实施例中，寄存器可以通过由处理器发出的写入操作来编程（例如，存储器映射的写入操作）。 因此，复位矢量地址可以在集成电路中可编程，并且可以不时地改变。
-
53.发明申请公开(公告)号：US20140089617A1
公开(公告)日：2014-03-27
申请号：US13626546
申请日：2012-09-25
Applicant: APPLE INC.
Inventor： R. Stephen Polzin , James B. Keller , Gerard R. Williams, III
IPC: G06F12/14
CPC classification number: G06F12/14 , G06F12/1441 , G06F21/575 , G06F21/74
Abstract: An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the rest of the SOC (e.g. one or more central processing units (CPUs) in the SOC, or application processors (APs) in the SOC). Access to the SEP may be strictly controlled by hardware. For example, a mechanism in which the CPUs/APs can only access a mailbox location in the SEP is described. The CPU/AP may write a message to the mailbox, which the SEP may read and respond to. The SEP may include one or more of the following in some embodiments: secure key management using wrapping keys, SEP control of boot and/or power management, and separate trust zones in memory.
Abstract translation: SOC实现安全飞地处理器（SEP）。 SEP可以包括处理器和一个或多个安全外设。 SEP可以与SOC的其余部分隔离（例如SOC中的一个或多个中央处理单元（CPU），或SOC中的应用处理器（AP））。 对SEP的访问可以由硬件严格控制。 例如，描述了CPU / AP仅能访问SEP中的邮箱位置的机制。 CPU / AP可以向邮箱写入消息，SEP可以读取并响应。 在一些实施例中，SEP可以包括以下一个或多个：使用包装密钥的安全密钥管理，引导和/或电源管理的SEP控制以及存储器中的单独的信任区域。
-
公开(公告)号：US20230064526A1
公开(公告)日：2023-03-02
申请号：US17657506
申请日：2022-03-31
Applicant: Apple Inc.
Inventor： Sagi Lahav , Lital Levy - Rubin , Gaurav Garg , Gerard R. Williams, III , Samer Nassar , Per H. Hammarlund , Harshavardhan Kaushikkar , Srinivasa Rangan Sridharan , Jeff Gonion
Abstract: Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include one or more queues and a transaction pipeline. The I/O agent circuit may issue, to the transaction pipeline from a queue of the one or more queues, a transaction of a series of transactions enqueued in a particular order. The I/O agent circuit may generate, at the transaction pipeline, a determination to return the transaction to the queue based on a detection of one or more conditions being satisfied. Based on the determination, the I/O agent circuit may reject, at the transaction pipeline, up to a threshold number of transactions that issued from the queue after the transaction issued. The I/O agent circuit may insert the transaction at a head of the queue such that the transaction is enqueued at the queue sequentially first for the series of transactions according to the particular order.
-
公开(公告)号：US20220137692A1
公开(公告)日：2022-05-05
申请号：US17528380
申请日：2021-11-17
Applicant: Apple Inc.
Inventor： Joseph T. DiBene, II , Inder M. Sodhi , Keith Cox , Gerard R. Williams, III
IPC: G06F1/3206 , G06F1/3203 , G06F1/3296
Abstract: In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g., with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.
-
Patent Agency Ranking
公开(公告)号：US11204636B2
公开(公告)日：2021-12-21
申请号：US16519347
申请日：2019-07-23
Applicant: Apple Inc.
Inventor： Joseph T. DiBene, II , Inder M. Sodhi , Keith Cox , Gerard R. Williams, III
IPC: G06F1/3206 , G06F1/3203 , G06F1/3296
Abstract: In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g. with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.
-
公开(公告)号：US20200034145A1
公开(公告)日：2020-01-30
申请号：US16043772
申请日：2018-07-24
Applicant: Apple Inc.
Inventor： Eric Bainville , Jeffry E. Gonion , Ali Sazegari , Gerard R. Williams, III
Abstract: In an embodiment, a computation engine is configured to perform vector multiplications, producing either vector results or outer product (matrix) results. The instructions provided to the computation engine specify a matrix mode or a vector mode for the instructions. The computation engine performs the specified operation. The computation engine may perform numerous computations in parallel, in an embodiment. In an embodiment, the instructions may also specify an offset with the input memories, providing additional flexibility in the location of operands. More particularly, the computation engine may be configured to perform numerous multiplication operations in parallel and to accumulate results in a result memory, performing multiply-accumulate operations for each matrix/vector element in the targeted locations of the output memory.
-
公开(公告)号：US10437595B1
公开(公告)日：2019-10-08
申请号：US15070435
申请日：2016-03-15
Applicant: Apple Inc.
Inventor： Pradeep Kanapathipillai , Stephan G. Meier , Gerard R. Williams, III , Mridul Agarwal , Kulin N. Kothari
Abstract: Systems, apparatuses, and methods for optimizing a load-store dependency predictor (LSDP). When a younger load instruction is issued before an older store instruction and the younger load is dependent on the older store, the LSDP is trained on this ordering violation. A replay/flush indicator is stored in a corresponding entry in the LSDP to indicate whether the ordering violation resulted in a flush or replay. On subsequent executions, a dependency may be enforced for the load-store pair if a confidence counter is above a threshold, with the threshold varying based on the status of the replay/flush indicator. If a given load matches on multiple entries in the LSDP, and if at least one of the entries has a flush indicator, then the given load may be marked as a multimatch case and forced to wait to issue until all older stores have issued.
-
公开(公告)号：US10423209B2
公开(公告)日：2019-09-24
申请号：US15430699
申请日：2017-02-13
Applicant: Apple Inc.
Inventor： Joseph T. DiBene, II , Inder M. Sodhi , Keith Cox , Gerard R. Williams, III
IPC: G06F9/00 , G06F1/3206 , G06F1/3296 , G06F1/3203
Abstract: In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g. with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.
-
公开(公告)号：US20180129271A1
公开(公告)日：2018-05-10
申请号：US15866014
申请日：2018-01-09
Applicant: Apple Inc.
Inventor： David J. Williamson , Gerard R. Williams, III
CPC classification number: G06F1/3293 , G06F1/3206 , G06F1/3234 , G06F1/3287 , G06F1/3296 , G06F9/461 , Y02B70/123 , Y02D10/172 , Y02D10/30
Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, but may have higher minimum voltage at which it operates correctly. Another core may be implemented at a lower maximum performance, but may be optimized for efficiency and may operate correctly at a lower minimum voltage. The processor may support multiple processor states (PStates). Each PState may specify an operating point and may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core.
-
-
-
-
-
-
-
-
-
Search Results
68
records
(took 0.02 seconds)
