公开(公告)号：US20070090722A1

公开(公告)日：2007-04-26

申请号：US10548852

申请日：2004-03-11

申请人： Jong-I Mou ,  Chi-Te Chin

发明人： Jong-I Mou ,  Chi-Te Chin

IPC分类号： H02K5/00 ,  H02N1/00

CPC分类号： H02N1/008 ,  B81B3/0062 ,  B81B2201/037

摘要： A planar micro parallel-link mechanism that provides fine planar motion to a platform in two translation directions and one rotation direction using comb-drive actuators with gear chain systems coupled to rack-and-pinions and struts. The micro parallel-link mechanism has a large operating envelope and can be fabricated using surface micromachining techniques. The kinematic and dynamic analyses of the micro parallel-link mechanism are integrated with closed-loop control system to monitor and supervise the position and velocity of the micro mechanism with three degree-of freedom motions. Methods of depositing and building miniaturized tools and parts on the platform are also disclosed to provide the basic building block for a number of products applicable for nano technology, sensor, actuators, and biotechnology applications.

摘要翻译： 一种平面微平行连杆机构，它使用梳齿驱动致动器，在齿轮链系统与齿条和小齿轮和支柱相连的情况下，在两个平移方向和一个旋转方向上向平台提供精细的平面运动。 微型平行连杆机构具有较大的操作范围，并且可以使用表面微加工技术制造。 微型并联机构的动力学和动力学分析与闭环控制系统集成，以三自由度运动来监测和监督微机构的位置和速度。 还公开了在平台上沉积和构建小型化工具和部件的方法，以提供适用于纳米技术，传感器，致动器和生物技术应用的许多产品的基本构建块。

公开(公告)号：US09477219B2

公开(公告)日：2016-10-25

申请号：US12731348

申请日：2010-03-25

申请人： Chih-Wei Hsu ,  Jin-Ning Sung ,  Shin-Rung Lu ,  Jong-I Mou

发明人： Chih-Wei Hsu ,  Jin-Ning Sung ,  Shin-Rung Lu ,  Jong-I Mou

IPC分类号： G05B19/418

CPC分类号： G05B19/41875 ,  G05B2219/32017 ,  G05B2219/32189 ,  G05B2219/45031 ,  Y02P90/22

摘要： A method of semiconductor fabrication is provided. The method includes providing a model for a device parameter of a wafer as a function of first and second process parameters. The first and second process parameters correspond to different wafer characteristics, respectively. The method includes deriving target values of the first and second process parameters based on a specified target value of the device parameter. The method includes performing a first fabrication process in response to the target value of the first process parameter. The method includes measuring an actual value of the first process parameter thereafter. The method includes updating the model using the actual value of the first process parameter. The method includes deriving a revised target value of the second process parameter using the updated model. The method includes performing a second fabrication process in response to the revised target value of the second process parameter.

摘要翻译： 提供了一种半导体制造方法。 该方法包括提供晶片的器件参数的模型作为第一和第二工艺参数的函数。 第一和第二工艺参数分别对应于不同的晶片特性。 该方法包括基于设备参数的指定目标值导出第一和第二处理参数的目标值。 该方法包括响应于第一过程参数的目标值执行第一制造过程。 该方法包括此后测量第一处理参数的实际值。 该方法包括使用第一过程参数的实际值更新模型。 该方法包括使用更新的模型导出第二过程参数的修正目标值。 该方法包括响应于修改的第二过程参数的目标值执行第二制造过程。

公开(公告)号：US09026239B2

公开(公告)日：2015-05-05

申请号：US12793307

申请日：2010-06-03

申请人： Po-Feng Tsai ,  Yen-Di Tsen ,  Jo Fei Wang ,  Jong-I Mou

发明人： Po-Feng Tsai ,  Yen-Di Tsen ,  Jo Fei Wang ,  Jong-I Mou

IPC分类号： G06F19/00 ,  G05B11/01 ,  G05B17/02 ,  G05B15/00 ,  H01L21/66

CPC分类号： G05B17/02 ,  H01L22/20

摘要： A method of extending advanced process control (APC) models includes constructing an APC model table including APC model parameters of a plurality of products and a plurality of work stations. The APC model table includes empty cells and cells filled with existing APC model parameters. Average APC model parameters of the existing APC model parameters are calculated, and filled into the empty cells as initial values. An iterative calculation is performed to update the empty cells with updated values.

摘要翻译： 扩展先进过程控制（APC）模型的方法包括构建包括多个产品的APC模型参数和多个工作站的APC模型表。 APC模型表包括空单元格和填充有现有APC模型参数的单元格。 计算现有APC模型参数的平均APC模型参数，并作为初始值填充到空单元格中。 执行迭代计算以更新值更新空单元格。

公开(公告)号：US08793638B2

公开(公告)日：2014-07-29

申请号：US13559081

申请日：2012-07-26

申请人： Keuing Hui ,  Yen-Wei Cheng ,  Yen-Di Tsen ,  Jong-I Mou ,  Chin-Hsiang Lin

发明人： Keuing Hui ,  Yen-Wei Cheng ,  Yen-Di Tsen ,  Jong-I Mou ,  Chin-Hsiang Lin

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： The present disclosure describes a method of optimizing a design for manufacture (DFM) simulation. The method includes receiving an integrated circuit (IC) design data having a feature, receiving a process data having a parameter or a plurality of parameters, performing the DFM simulation, and optimizing the DFM simulation. The performing the DFM simulation includes generating a simulation output data using the IC design data and the process data. The optimizing the DFM simulation includes generating a performance index of the parameter or the plurality of parameters by the DFM simulation. The optimizing the DFM simulation includes adjusting the parameter or the plurality of parameters at outer loop, middle loop, and the inner loop. The optimizing the DFM simulation also includes locating a nadir of the performance index of the parameter or the plurality of parameters over a range of the parameter or the plurality of parameters.

摘要翻译： 本公开描述了优化用于制造（DFM）仿真的设计的方法。 该方法包括接收具有特征的集成电路（IC）设计数据，接收具有参数或多个参数的处理数据，执行DFM仿真和优化DFM仿真。 执行DFM模拟包括使用IC设计数据和过程数据生成模拟输出数据。 优化DFM模拟包括通过DFM仿真生成参数或多个参数的性能指标。 优化DFM模拟包括调整外循环，中间循环和内循环的参数或多个参数。 优化DFM模拟还包括在参数或多个参数的范围内定位参数或多个参数的性能指标的最低点。

公开(公告)号：US08406904B2

公开(公告)日：2013-03-26

申请号：US13033413

申请日：2011-02-23

申请人： Chih-Wei Hsu ,  Yen-Di Tsen ,  Jong-I Mou

发明人： Chih-Wei Hsu ,  Yen-Di Tsen ,  Jong-I Mou

IPC分类号： G05B13/02 ,  G06F19/00

CPC分类号： G05B19/41865 ,  G05B2219/32135 ,  G05B2219/32267 ,  G05B2219/45031 ,  Y02P90/20 ,  Y02P90/265

摘要： The present disclosure provides a method. The method includes gathering advanced process control (APC) data from a subset of available wafers and a subset of available processing chambers. The method includes establishing a matrix that contains a plurality of cells. The cells each correspond to one of the available wafers and one of the available processing chambers. The matrix is partially filled by populating cells for which the APC data has been gathered. The method includes determining a plurality of chamber-coverage-rate (CCR) parameters associated with the matrix. The method includes optimizing the CCR parameters through an iteration process to obtain optimized CCR parameters. The method includes predicting an APC data value for a designated cell of the matrix based on the optimized CCR parameters. The designated cell is an empty cell before the predicting and is populated by the predicting.

摘要翻译： 本公开提供了一种方法。 该方法包括从可用晶片的子集和可用处理室的子集中收集先进的过程控制（APC）数据。 该方法包括建立包含多个单元的矩阵。 每个单元对应于可用晶片之一和可用处理室之一。 通过填充已经收集了APC数据的单元格来部分填充矩阵。 该方法包括确定与矩阵相关联的多个腔室覆盖率（CCR）参数。 该方法包括通过迭代过程优化CCR参数以获得优化的CCR参数。 该方法包括基于优化的CCR参数预测矩阵的指定小区的APC数据值。 指定的单元格是在预测之前的空单元格，并由预测填充。

公开(公告)号：US20100210041A1

公开(公告)日：2010-08-19

申请号：US12370746

申请日：2009-02-13

申请人： Chun-Lin Chang ,  Hsin-Hsien Wu ,  Zin-Chang Wei ,  Chi-Ming Yang ,  Chyi-Shyuan Chern ,  Jun-Lin Yeh ,  Jih-Jse Lin ,  Jo-Fei Wang ,  Ming-Yu Fan ,  Jong-I Mou

发明人： Chun-Lin Chang ,  Hsin-Hsien Wu ,  Zin-Chang Wei ,  Chi-Ming Yang ,  Chyi-Shyuan Chern ,  Jun-Lin Yeh ,  Jih-Jse Lin ,  Jo-Fei Wang ,  Ming-Yu Fan ,  Jong-I Mou

IPC分类号： H01L21/66 ,  H01L21/306 ,  H01L21/26 ,  H01L21/265

CPC分类号： H01L22/20 ,  H01L21/67248 ,  H01L21/67253 ,  H01L22/12

摘要： An apparatus includes a process chamber configured to perform an ion implantation process. A cooling platen or electrostatic chuck is provided within the process chamber. The cooling platen or electrostatic chuck is configured to support a semiconductor wafer. The cooling platen or electrostatic chuck has a plurality of temperature zones. Each temperature zone includes at least one fluid conduit within or adjacent to the cooling platen or electrostatic chuck. At least two coolant sources are provided, each fluidly coupled to a respective one of the fluid conduits and configured to supply a respectively different coolant to a respective one of the plurality of temperature zones during the ion implantation process. The coolant sources include respectively different chilling or refrigeration units.

摘要翻译： 一种装置包括被配置为执行离子注入工艺的处理室。 在处理室内设有冷却台板或静电吸盘。 冷却台板或静电卡盘构造成支撑半导体晶片。 冷却台板或静电卡盘具有多个温度区域。 每个温度区域包括在冷却压板或静电卡盘内或附近的至少一个流体导管。 提供至少两个冷却剂源，每个冷却剂源流体耦合到相应的一个流体管道，并且构造成在离子注入过程期间将分别不同的冷却剂供应到多个温度区中的相应的一个温度区。 冷却剂源分别包括不同的冷却或制冷装置。

公开(公告)号：US09727049B2

公开(公告)日：2017-08-08

申请号：US13603079

申请日：2012-09-04

申请人： Chia-Tong Ho ,  Po-Feng Tsai ,  Jung-Chang Chen ,  Tze-Liang Lee ,  Jo Fei Wang ,  Jong-I Mou ,  Chin-Hsiang Lin

发明人： Chia-Tong Ho ,  Po-Feng Tsai ,  Jung-Chang Chen ,  Tze-Liang Lee ,  Jo Fei Wang ,  Jong-I Mou ,  Chin-Hsiang Lin

IPC分类号： G06F19/00 ,  G05B19/4065

CPC分类号： G05B19/4065 ,  G05B2219/37252 ,  G05B2219/45031

摘要： The present disclosure provides various methods for tool condition monitoring, including systems for implementing such monitoring. An exemplary method includes receiving data associated with a process performed on wafers by an integrated circuit manufacturing process tool; and monitoring a condition of the integrated circuit manufacturing process tool using the data. The monitoring includes evaluating the data based on an abnormality identification criterion, an abnormality filtering criterion, and an abnormality threshold to determine whether the data meets an alarm threshold. The method may further include issuing an alarm when the data meets the alarm threshold.

公开(公告)号：US09000798B2

公开(公告)日：2015-04-07

申请号：US13495421

申请日：2012-06-13

申请人： Jui-Long Chen ,  Chien-Chih Liao ,  Tseng Chin Lo ,  Hui-Yun Chao ,  Ta-Yung Lee ,  Jong-I Mou ,  Chin-Hsiang Lin

发明人： Jui-Long Chen ,  Chien-Chih Liao ,  Tseng Chin Lo ,  Hui-Yun Chao ,  Ta-Yung Lee ,  Jong-I Mou ,  Chin-Hsiang Lin

IPC分类号： G01R31/02 ,  G01R31/28 ,  H01L23/544

CPC分类号： G01R1/07364 ,  G01R1/06705 ,  G01R31/2887 ,  G01R31/2891 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/00 ,  H01L2924/0002

摘要： A system and method for aligning a probe, such as a wafer-level test probe, with wafer contacts is disclosed. An exemplary method includes receiving a wafer containing a plurality of alignment contacts and a probe card containing a plurality of probe points at a wafer test system. A historical offset correction is received. Based on the historical offset correct, an orientation value for the probe card relative to the wafer is determined. The probe card is aligned to the wafer using the orientation value in an attempt to bring a first probe point into contact with a first alignment contact. The connectivity of the first probe point and the first alignment contact is evaluated. An electrical test of the wafer is performed utilizing the aligned probe card, and the historical offset correction is updated based on the orientation value.

摘要翻译： 公开了一种用于将诸如晶片级测试探针的探针与晶片接触件对准的系统和方法。 一种示例性方法包括在晶片测试系统处接收包含多个对准触点的晶片和包含多个探针点的探针卡。 接收到历史偏移校正。 基于历史偏移校正，确定探针卡相对于晶片的取向值。 使用取向值将探针卡与晶片对准，以试图使第一探针点与第一对准触点接触。 评估第一探针点和第一对准接触点的连接性。 使用对准的探针卡进行晶片的电气测试，并且基于取向值更新历史偏移校正。

公开(公告)号：US08627251B2

公开(公告)日：2014-01-07

申请号：US13455186

申请日：2012-04-25

申请人： Jui-Long Chen ,  Hui-Yun Chao ,  Yen-Di Tsen ,  Jong-I Mou

发明人： Jui-Long Chen ,  Hui-Yun Chao ,  Yen-Di Tsen ,  Jong-I Mou

IPC分类号： G06F17/50

CPC分类号： H01L22/20 ,  H01L22/10 ,  H01L22/12 ,  H01L22/14 ,  H01L2924/0002 ,  Y10T29/41 ,  H01L2924/00

摘要： A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.

摘要翻译： 提供了一种自动检测半导体晶片工艺的故障模式的系统和方法。 该方法包括接收从测试多个半导体晶片收集的测试数据集，为每个晶片形成相应的晶片图，确定每个相应的晶片图是否包括一个或多个相应的对象，选择被确定为包括的晶片图 一个或多个相应的对象，选择一个或多个对象索引，用于在每个相应的选定的晶片图中选择相应的对象，确定每个相应选择的晶片图中的多个对象索引值，在每个相应选定的晶片图中选择一个对象， 各个所选晶片中的每一个的相应特征，对各个所选晶片图中的每一个分类各自的图案，并使用相应的晶片指纹来调整半导体制造工艺的一个或多个参数。

公开(公告)号：US20130335109A1

公开(公告)日：2013-12-19

申请号：US13495421

申请日：2012-06-13

申请人： Jui-Long Chen ,  Chien-Chih Liao ,  Tseng Chin Lo ,  Hui-Yun Chao ,  Ta-Yung Lee ,  Jong-I Mou ,  Chin-Hsiang Lin

发明人： Jui-Long Chen ,  Chien-Chih Liao ,  Tseng Chin Lo ,  Hui-Yun Chao ,  Ta-Yung Lee ,  Jong-I Mou ,  Chin-Hsiang Lin

IPC分类号： G01R31/26 ,  H01L29/06

CPC分类号： G01R1/07364 ,  G01R1/06705 ,  G01R31/2887 ,  G01R31/2891 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/00 ,  H01L2924/0002

摘要： A system and method for aligning a probe, such as a wafer-level test probe, with wafer contacts is disclosed. An exemplary method includes receiving a wafer containing a plurality of alignment contacts and a probe card containing a plurality of probe points at a wafer test system. A historical offset correction is received. Based on the historical offset correct, an orientation value for the probe card relative to the wafer is determined. The probe card is aligned to the wafer using the orientation value in an attempt to bring a first probe point into contact with a first alignment contact. The connectivity of the first probe point and the first alignment contact is evaluated. An electrical test of the wafer is performed utilizing the aligned probe card, and the historical offset correction is updated based on the orientation value.

摘要翻译： 公开了一种用于将诸如晶片级测试探针之类的探针与晶片接点对准的系统和方法。 一种示例性方法包括在晶片测试系统处接收包含多个对准触点的晶片和包含多个探针点的探针卡。 接收到历史偏移校正。 基于历史偏移校正，确定探针卡相对于晶片的取向值。 使用取向值将探针卡与晶片对准，以试图使第一探针点与第一对准触点接触。 评估第一探针点和第一对准接触点的连接性。 使用对准的探针卡进行晶片的电气测试，并且基于取向值更新历史偏移校正。