公开(公告)号：US20070198808A1

公开(公告)日：2007-08-23

申请号：US11276236

申请日：2006-02-20

申请人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Sebastian Ventrone ,  Keith Williams

发明人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Sebastian Ventrone ,  Keith Williams

IPC分类号： G06F15/00

CPC分类号： G06F9/3869 ,  G11C27/026

摘要： A system, method and program product for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.

摘要翻译： 公开了一种用于保持处理器流水线架构的逻辑状态的系统，方法和程序产品。 比较器位于处理器流水线架构的两个阶段之间。 存储电容器耦合在比较器的存储节点和地之间以存储两个阶段的早期阶段的输出。 提供了与早期输出值相同的参考逻辑。 逻辑存储和分配装置耦合在参考逻辑和比较器的参考节点之间，以便在参考节点处产生逻辑，该逻辑是参考逻辑的一小部分，并且保留存储在存储器上的信息的逻辑状态 电容器。 提供进一步的机制来确定存储在逻辑存储和分配装置中的数据的有效性。

公开(公告)号：US20070188664A1

公开(公告)日：2007-08-16

申请号：US11276130

申请日：2006-02-15

申请人： Ahmed Ginawi ,  Casey Grant ,  Christopher Ro ,  Sebastian Ventrone

发明人： Ahmed Ginawi ,  Casey Grant ,  Christopher Ro ,  Sebastian Ventrone

IPC分类号： H04N5/50 ,  H04N5/66 ,  H04N5/44

CPC分类号： H04N5/50 ,  H04N7/163 ,  H04N21/4383 ,  H04N21/4394 ,  H04N21/44008 ,  H04N21/472 ,  H04N21/812

摘要： Systems for switching a displayed signal for a display between a plurality of signals are disclosed. In one embodiment, the system includes a microcontroller; a chooser for choosing a primary signal from a plurality of program-variable signals at the microcontroller; a monitor tuner coupled to the microcontroller for tuning the primary signal during switching of the displayed signal from the primary signal to a secondary signal; a detector coupled to the monitor tuner and the microcontroller for detecting a predetermined condition in the primary signal; and a selector coupled to the microcontroller for switching the displayed signal from the secondary signal to the primary signal upon occurrence of the predetermined condition. A user can switch between signals such as television channels or other dedicated functions without the risk of missing a portion of the program material.

摘要翻译： 公开了用于在多个信号之间切换用于显示的显示信号的系统。 在一个实施例中，该系统包括微控制器; 用于在微控制器处从多个可编程信号中选择主信号的选择器; 耦合到微控制器的监视器调谐器，用于在将所显示的信号从主信号切换到辅助信号期间调谐主信号; 耦合到所述监视器调谐器和所述微控制器的检测器，用于检测所述主信号中的预定条件; 以及耦合到微控制器的选择器，用于在发生预定条件时将显示的信号从次级信号切换到主信号。 用户可以在诸如电视频道或其他专用功能的信号之间切换，而不会丢失节目素材的一部分。

公开(公告)号：US20070162792A1

公开(公告)日：2007-07-12

申请号：US11275536

申请日：2006-01-12

申请人： Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Sebastian Ventrone ,  Paul Zuchowski

发明人： Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Sebastian Ventrone ,  Paul Zuchowski

IPC分类号： G01R31/26 ,  G11C29/00

CPC分类号： G01R31/31718 ,  G11C17/14 ,  G11C29/88 ,  H03K19/17764 ,  H03K19/17796

摘要： A method for increasing the manufacturing yield of field programmable gate arrays (FPGAS) or other programmable logic devices (PLDs). An FPGA or other PLD is formed in several sections, each of the sections having its own power bus and input/output connections. Each section of the FPGA or other PLD is tested to identify defects in the FPGA or other PLD. The FPGA or other PLD is sorted according to whether the section has an acceptable number of defects. An assigned unique number for the FPGA or other PLD chip or part identifies it as partially good. Software for execution and configuring the FPGA or other PLD may use the unique number for programming only the identified functional sections of the FPGA or other PLD. The result is an increase in yield as partially good FPGAs or other PLDs may still be utilized.

摘要翻译： 一种提高现场可编程门阵列（FPGAS）或其他可编程逻辑器件（PLD）的制造成品率的方法。 FPGA或其他PLD形成在几个部分中，每个部分都有自己的电源总线和输入/输出连接。 测试FPGA或其他PLD的每个部分，以识别FPGA或其他PLD中的缺陷。 FPGA或其他PLD根据该部分是否具有可接受的缺陷数量进行排序。 为FPGA或其他PLD芯片或部件分配的唯一编号将其识别为部分良好。 用于执行和配置FPGA或其他PLD的软件可以使用唯一编号仅对FPGA或其他PLD的已识别功能部分进行编程。 结果是产量增加，部分好的FPGA或其他PLD仍然可以被利用。

公开(公告)号：US20070101304A1

公开(公告)日：2007-05-03

申请号：US11163750

申请日：2005-10-28

申请人： Richard Bell ,  Wilson Skipwith ,  Sebastian Ventrone

发明人： Richard Bell ,  Wilson Skipwith ,  Sebastian Ventrone

IPC分类号： G06F17/50 ,  H01L25/00 ,  H03K19/00

CPC分类号： H03K3/037

摘要： A fast/slow state machine latch is provided that generates fast and slow select signals for a single toggle, low power multiplexer circuit. In accordance with an embodiment of the present invention, the fast/slow state machine latch includes a first latch with a delayed output, a second latch with an undelayed output, an inverter for coupling the delayed output of the first latch to an input of the second latch, and an exclusive-OR (XOR) gate coupled to the delayed output of the first latch and a data input, an output of the XOR gate coupled to an input of the first latch. A method for incorporating low power multiplexer circuits into a circuit design with minimal input from a circuit designer is also provided.

摘要翻译： 提供了一种快速/慢速状态机锁存器，为单个切换低功率多路复用器电路产生快速和慢速选择信号。 根据本发明的实施例，快速/慢速状态机锁存器包括具有延迟输出的第一锁存器，具有未延迟输出的第二锁存器，用于将第一锁存器的延迟输出耦合到第一锁存器的输入端的反相器 第二锁存器和耦合到第一锁存器的延迟输出的异或（XOR）门和数据输入，XOR门的输出耦合到第一锁存器的输入。 还提供了一种将低功率多路复用器电路并入到具有来自电路设计器的最小输入的电路设计中的方法。

公开(公告)号：US20070075731A1

公开(公告)日：2007-04-05

申请号：US11163015

申请日：2005-09-30

申请人： Igor Arsovski ,  Hayden Cranford ,  Joseph Iadanza ,  Sebastian Ventrone

发明人： Igor Arsovski ,  Hayden Cranford ,  Joseph Iadanza ,  Sebastian Ventrone

IPC分类号： H03K19/003

CPC分类号： H03K19/00346

摘要： An integrated circuit device includes functional logic, an anti-noise machine, and state monitoring points providing the anti-noise machine with an interface to the functional logic for monitoring states of the functional logic. The anti-noise machine includes indicia defining noise precursor states for the functional logic, and recognition logic coupled to the state monitoring points. The anti-noise machine is operable to generate anti-noise responsive to the recognition logic detecting in the functional logic noise precursor states matching the indicia.

摘要翻译： 集成电路设备包括功能逻辑，抗噪声机器和状态监测点，其为抗噪声机器提供与用于监视功能逻辑状态的功能逻辑的接口。 抗噪声机器包括定义用于功能逻辑的噪声前导状态的标记，以及耦合到状态监测点的识别逻辑。 抗噪声机器可操作以响应于与标记匹配的功能逻辑噪声前导状态中的识别逻辑检测产生抗噪声。

公开(公告)号：US20060190744A1

公开(公告)日：2006-08-24

申请号：US10906476

申请日：2005-02-22

申请人： Rafael Blanco ,  John Cohn ,  Kenneth Goodnow ,  Douglas Stout ,  Sebastian Ventrone

发明人： Rafael Blanco ,  John Cohn ,  Kenneth Goodnow ,  Douglas Stout ,  Sebastian Ventrone

IPC分类号： G06F1/26

CPC分类号： G06F1/3287 ,  G06F1/26 ,  G06F1/3203 ,  Y02D10/171

摘要： An integrated circuit has a power grid and a set of independently switchable voltage islands, together with a system and method for measuring the voltage and history of the voltage on the power grid to determine the correct time to allow a large capacitive load (such as a voltage island) to be switched on to or off the power grid.

摘要翻译： 集成电路具有电网和一组可独立切换的电压岛，以及用于测量电网电压和历史的系统和方法，以确定允许大容性负载（例如， 电压岛）被接通或断开电网。

公开(公告)号：US20060082398A1

公开(公告)日：2006-04-20

申请号：US11275773

申请日：2006-01-27

申请人： Nancy Pratt ,  Sebastian Ventrone

发明人： Nancy Pratt ,  Sebastian Ventrone

IPC分类号： H03B21/00

CPC分类号： G06F1/04 ,  H03K5/1504 ,  H03K19/00361

摘要： A digital system and a method for operating the same. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.

摘要翻译： 数字系统及其操作方法。 数字系统包括（a）第一逻辑电路和第二逻辑电路，（b）第一寄存器，（c）第二寄存器，（d）第三寄存器，（e）时钟发生器电路，以及（f） 一个控制器电路。 第一逻辑电路能够获得第一数据并发送第二数据。 第二逻辑电路能够获得第二数据并发送第三数据。 时钟发生器电路能够在第一时间点断言（i）第一寄存器时钟信号，（ii）在第二时间点的第二寄存器时钟信号，以及（iii）第三时间点的第三寄存器时钟信号 。 控制器电路能够（i）确定第四时间点，（ii）确定第五时间点，（iii）控制时钟发生器电路以断言第二寄存器时钟信号。

公开(公告)号：US20060070016A1

公开(公告)日：2006-03-30

申请号：US11272884

申请日：2005-11-14

申请人： Kenneth Goodnow ,  Clarence Ogilvie ,  Sebastian Ventrone

发明人： Kenneth Goodnow ,  Clarence Ogilvie ,  Sebastian Ventrone

IPC分类号： G06F17/50 ,  H03K19/173 ,  H03K19/00 ,  G06F7/38 ,  H01L25/00

CPC分类号： G06F17/5054 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

摘要： A structure comprising an FPGA (Field-Programmable Gate Array) for relieving bottlenecks, and a method for operating the structure. The FPGA comprises multiple FPGA elements each of which includes a CLB (Configurable Logic Block), an instruction queue, and a data buffer. One functional block after another (separate from one another) can be formed in the FPGA via a first local IO (Input/Output) circuit and moved to a second local IO circuit. Within each functional block, a mapped logic location function calculates the direction, distance, and the time for the step from the current location of the functional block stored in a mapped location register, and the destination stored in a mapped destination register, and the time allowed for the movement, and stores the direction and distance of the step in the mapped movement register. Then, the functional block moves according the direction and distance stored in the mapped movement register.

公开(公告)号：US20050121698A1

公开(公告)日：2005-06-09

申请号：US10731296

申请日：2003-12-09

申请人： Christopher Reynolds ,  Sebastian Ventrone ,  Angela Weil

发明人： Christopher Reynolds ,  Sebastian Ventrone ,  Angela Weil

IPC分类号： H01L27/10 ,  H01L27/118 ,  H03K19/177

CPC分类号： G06F17/5068 ,  H01L27/11803

摘要： A field programmable gate array is described for use in a semiconductor chip such as a VLSI chip. The array is provided with variable wire-through porosity to allow for optimum chip-level routing through the array. This is achieved by dividing the array into blocks which can be individually assessed for required porosity. Then blocks that have been prefabricated with differing porosities are placed in the macro to optimize local chip level routing. The routing of wires is determined by developing a chip floor plan to include early timing allocation and a proposed placement of the array. The floor plan is then overlaid with critical logical wiring nets. From this, an initial selection of blocks is made based on proposed wiring density, and the macro is assembled with the blocks strategically placed therein. The procedure is likewise applicable to other types of densely obstructed cores embedded with a chip.

摘要翻译： 描述了用于诸如VLSI芯片的半导体芯片中的现场可编程门阵列。 该阵列具有可变的线穿孔孔，以允许通过阵列的最佳芯片级布线。 这是通过将阵列划分成可以单独评估所需孔隙度的块来实现的。 然后将具有不同孔隙度的预制块放置在宏中以优化本地芯片级布线。 通过开发芯片平面图来确定导线的布线，以包括早期的时序分配和阵列的建议放置。 然后将平面图重叠在关键的逻辑布线网上。 由此，基于所提出的布线密度进行块的初始选择，并且宏与被策略地放置在其中的块组装。 该程序同样适用于嵌入芯片的其他类型的密封阻塞芯。

公开(公告)号：US20050120323A1

公开(公告)日：2005-06-02

申请号：US10725712

申请日：2003-12-02

申请人： Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Jack Smith ,  Sebastian Ventrone

发明人： Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Jack Smith ,  Sebastian Ventrone

IPC分类号： G06F17/50 ,  H03K19/00

CPC分类号： G06F17/5054

摘要： A method and system for modifying the function of a state machine having a programmable logic device. The method including: (a) modifying a high-level design of the state machine to obtain a modified high-level design of the state machine with a modified function; (b) generating a programmable logic device netlist from differences in the high-level design and the modified design; and (c) installing the modified function into the state machine by programming the programmable logic device based on the programmable logic device netlist.

摘要翻译： 一种用于修改具有可编程逻辑器件的状态机的功能的方法和系统。 该方法包括：（a）修改状态机的高级设计，以获得具有修改功能的状态机修改后的高级设计; （b）从高级设计和改进设计的差异中产生可编程逻辑器件网表; 和（c）通过基于可编程逻辑器件网表对可编程逻辑器件进行编程来将修改后的功能安装到状态机中。