公开(公告)号：US20070198808A1

公开(公告)日：2007-08-23

申请号：US11276236

申请日：2006-02-20

申请人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Sebastian Ventrone ,  Keith Williams

发明人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Sebastian Ventrone ,  Keith Williams

IPC分类号： G06F15/00

CPC分类号： G06F9/3869 ,  G11C27/026

摘要： A system, method and program product for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.

摘要翻译： 公开了一种用于保持处理器流水线架构的逻辑状态的系统，方法和程序产品。 比较器位于处理器流水线架构的两个阶段之间。 存储电容器耦合在比较器的存储节点和地之间以存储两个阶段的早期阶段的输出。 提供了与早期输出值相同的参考逻辑。 逻辑存储和分配装置耦合在参考逻辑和比较器的参考节点之间，以便在参考节点处产生逻辑，该逻辑是参考逻辑的一小部分，并且保留存储在存储器上的信息的逻辑状态 电容器。 提供进一步的机制来确定存储在逻辑存储和分配装置中的数据的有效性。

公开(公告)号：US20070228830A1

公开(公告)日：2007-10-04

申请号：US11278262

申请日：2006-03-31

申请人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Keith Williams ,  Sebastian Ventrone

发明人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Keith Williams ,  Sebastian Ventrone

IPC分类号： H02J3/00

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  H01L25/16 ,  H01L28/60 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19105 ,  Y02D10/171 ,  Y10T307/391

摘要： A method of reducing static power consumption in a low power electronic device. The electronic device including one or more power islands, each power island including: a local storage capacitor coupling a local power grid to a local ground grid; and a functional circuit connected between the local power grid and the local ground grid; a global storage capacitor coupling a global power grid to a global ground grid, each local ground grid connected to the global ground grid; one or more switches, each switch selectively connecting the global power grid to a single and different corresponding local power grid; and a power dispatch unit adapted to open and close the one or more switches.

摘要翻译： 一种降低低功率电子设备中的静态功耗的方法。 所述电子设备包括一个或多个功率岛，每个功率岛包括：将本地电网耦合到本地接地网的局部存储电容器; 以及连接在本地电网与本地接地网之间的功能电路; 将全球电网耦合到全球接地网的全球存储电容器，每个局部地电网连接到全球接地网; 一个或多个开关，每个开关选择性地将全局电网连接到单个和不同的相应的局部电网; 以及适于打开和关闭所述一个或多个开关的电力调度单元。

公开(公告)号：US20070258305A1

公开(公告)日：2007-11-08

申请号：US11279639

申请日：2006-04-13

申请人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Sebastian Ventrone ,  Keith Williams

发明人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Sebastian Ventrone ,  Keith Williams

IPC分类号： G11C7/00

CPC分类号： G06F12/121 ,  G06F12/122

摘要： A system, method and program product for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device. In a period that the data retaining device idles, charges in the charge storing device decay due to natural means. As such, a potential of the charge storing device may be used to indicate an amount of usage of the data retaining device. A comparison of the potentials of two charge storing devices coupled one-to-one to two data retaining devices may be used as a basis to determine a relative amount of usage of each of the two data retaining devices comparing to the other.

摘要翻译： 公开了一种用于确定数据保留装置的相对使用量的系统，方法和程序产品。 电荷存储装置以数据保持装置的使用触发电荷存储装置的充电的方式耦合到数据保持装置。 在数据保持装置闲置的期间，由于自然的手段，电荷存储装置中的电荷衰减。 因此，可以使用电荷存储装置的电位来指示数据保持装置的使用量。 可以使用将一对一耦合到两个数据保持装置的两个电荷存储装置的电位的比较作为确定两个数据保持装置中的每一个相对于另一个的相对使用量的基础。

公开(公告)号：US20080024197A1

公开(公告)日：2008-01-31

申请号：US11846578

申请日：2007-08-29

申请人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Keith Williams ,  Sebastian Ventrone

发明人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Keith Williams ,  Sebastian Ventrone

IPC分类号： G05F1/10

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  H01L25/16 ,  H01L28/60 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/19105 ,  Y02D10/171 ,  H01L2224/0401

摘要： A method of reducing static power consumption in a low power electronic device. The electronic device including one or more power islands, each power island including: a local storage capacitor coupling a local power grid to a local ground grid; and a functional circuit connected between the local power grid and the local ground grid; a global storage capacitor coupling a global power grid to a global ground grid, each local ground grid connected to the global ground grid; one or more switches, each switch selectively connecting the global power grid to a single and different corresponding local power grid; and a power dispatch unit adapted to open and close the one or more switches.

摘要翻译： 一种降低低功率电子设备中的静态功耗的方法。 所述电子设备包括一个或多个功率岛，每个功率岛包括：将本地电网耦合到本地接地网的局部存储电容器; 以及连接在本地电网与本地接地网之间的功能电路; 将全球电网耦合到全球接地网的全球存储电容器，每个局部地电网连接到全球接地网; 一个或多个开关，每个开关选择性地将全局电网连接到单个和不同的对应的局部电网; 以及适于打开和关闭所述一个或多个开关的电力调度单元。

公开(公告)号：US20070242507A1

公开(公告)日：2007-10-18

申请号：US11279507

申请日：2006-04-12

申请人： Kerry Bernstein ,  Kenneth Goodnow ,  Clearence Ogilvis ,  Sebastian Ventrone ,  Kelth Williams

发明人： Kerry Bernstein ,  Kenneth Goodnow ,  Clearence Ogilvis ,  Sebastian Ventrone ,  Kelth Williams

IPC分类号： G11C11/34

CPC分类号： G11C11/417

摘要： A system, method and program product for determining a history state of data in a data retaining device are disclosed. A state of a partially-depleted silicon-on-insulator (PD SOI) device coupled to a data retaining device is measured to indicate a body voltage of the PD SOI device. The body voltage of the PD SOI device may indicate, among others, how long the PD SOI device has been idling, which indirectly indicates how long data in the data retaining device has not been accessed. As such, the current invention may be used efficiently with, e.g., a cache replacement algorithm in a management of the data retaining device.

摘要翻译： 公开了一种用于确定数据保持装置中的数据的历史状态的系统，方法和程序产品。 耦合到数据保持装置的部分耗尽的绝缘体上硅（PD SOI）器件的状态被测量以指示PD SOI器件的体电压。 PD SOI器件的体电压可以指示PD SOI器件已经空转多长时间，这间接地指示数据保持器件中的数据未被访问多长时间。 因此，本发明可以在数据保留装置的管理中与例如高速缓存替换算法有效地使用。

公开(公告)号：US08729549B2

公开(公告)日：2014-05-20

申请号：US13533191

申请日：2012-06-26

申请人： Kerry Bernstein ,  Jerome L. Cann ,  Christopher M. Durham ,  Paul D. Kartschoke ,  Peter J. Klim ,  Donald L. Wheater

发明人： Kerry Bernstein ,  Jerome L. Cann ,  Christopher M. Durham ,  Paul D. Kartschoke ,  Peter J. Klim ,  Donald L. Wheater

IPC分类号： H01L23/58

CPC分类号： H01L22/32 ,  H01L21/4846 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/6835 ,  H01L2224/13005 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079

摘要： A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.

摘要翻译： 在外围测试结构衬底内形成通孔的多个外围测试结构衬底（PTSS）。 周边测试结构层和至少一个功能层通过通孔形成在多个PTSS的一侧上。 多个PTSS通孔中的另一侧在外围测试结构层和至少一个功能层的制造过程中暴露出来，以提供用于在整个制造顺序中测试各个层的功能性的接入点。 可以在完成所有至少一个功能层的所有制造之后执行C4键合。 不需要3D组装载体或C4载体衬底，因为外围测试结构衬底具有足够的机械强度以支撑外围测试结构层和至少一个功能层。

公开(公告)号：US20140043757A1

公开(公告)日：2014-02-13

申请号：US13568248

申请日：2012-08-07

申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie

发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie

IPC分类号： G05D23/00 ,  H05K7/20

CPC分类号： G05D23/1919 ,  G06F1/206 ,  H01L23/38 ,  H01L23/473 ,  H01L2224/16225 ,  H01L2924/1305 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K7/20272 ,  H05K7/20281 ,  H05K7/20518 ,  H01L2924/00

摘要： An integrated circuit chip having micro-channels formed in multiple regions of the integrated circuit chip and a method of cooling the integrated circuit chip. The method includes for any region of the multiple regions, allowing a coolant to flow through micro-channels of the region only when a temperature of the region exceed a first specified temperature and blocking the coolant from flowing through the micro-channels of the region when a temperature of the region is below a second specified temperature.

摘要翻译： 具有形成在集成电路芯片的多个区域中的微通道的集成电路芯片和冷却集成电路芯片的方法。 该方法包括对于多个区域的任何区域，只有当该区域的温度超过第一规定温度并且阻止冷却剂流过该区域的微通道时，冷却剂才能流过该区域的微通道， 该区域的温度低于第二规定温度。

公开(公告)号：US08575964B2

公开(公告)日：2013-11-05

申请号：US13426776

申请日：2012-03-22

申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  John Sargis, Jr. ,  Sebastian T. Ventrone ,  Charles S. Woodruff

发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  John Sargis, Jr. ,  Sebastian T. Ventrone ,  Charles S. Woodruff

IPC分类号： H03K19/00

CPC分类号： H03K19/0966 ,  H03K19/0013

摘要： Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the local reference voltage is below a local voltage threshold. Activity in the local combinatorial logic structure causes the local reference voltage to drop below the local reference voltage independently of changes in the global reference voltage causing the comparator to output the clock pulse (with sufficient delay to allow the logic results to be stored in the registers only after setup times have been met in the local logic devices). This eliminates the need for a clock distribution tree, thereby saving power when there is no activity in the local combinatorial logic structure.

摘要翻译： 电路的局部逻辑区域包括电连接到局部电阻电压电路的本地比较器，局部电阻接地电路和局部寄存器结构。 当本地参考电压低于本地电压阈值时，本地比较器会向本地寄存器结构提供时钟脉冲。 本地组合逻辑结构中的活动导致本地参考电压低于局部参考电压，而与全局参考电压的变化无关，导致比较器输出时钟脉冲（具有足够的延迟以允许逻辑结果存储在寄存器中 只有在本地逻辑设备中已经满足设置时间之后）。 这消除了对时钟分配树的需要，从而在局部组合逻辑结构中没有活动时节省功率。

公开(公告)号：US08343814B2

公开(公告)日：2013-01-01

申请号：US12542235

申请日：2009-08-17

申请人： Robert J. Bucki ,  Jagreet S. Atwal ,  Joseph S. Barnes ,  Kerry Bernstein ,  Eric Robinson

发明人： Robert J. Bucki ,  Jagreet S. Atwal ,  Joseph S. Barnes ,  Kerry Bernstein ,  Eric Robinson

IPC分类号： H01L21/335

CPC分类号： H01L25/0657 ,  G11C15/00 ,  H01L21/6835 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2221/68368 ,  H01L2224/24226 ,  H01L2224/80896 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/04953 ,  H01L2924/10329 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

摘要： A multi-ported CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-ported CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the multi-port CAM can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-port CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays. Each compare match line and data bit line has the length associated with a simple two-dimensional Static Random Access Memory (SRAM) cell array.

摘要翻译： 提供了一种多移动CAM单元，其中增加行程距离的负面影响已经大大减少。 多端口CAM单元在本发明中是通过利用三维积分来实现的，其中多个有源电路层是垂直堆叠的，并且使用垂直排列的互连将器件从堆叠层之一连接到另一层叠层中的另一个器件 。 通过垂直堆叠具有垂直排列的互连的多个有源电路层，多端口CAM的每个比较端口可以在主数据存储单元上方或下方的单独层上实现。 这允许在与标准随机存取存储器（RAM）单元相同的区域覆盖范围内实现多端口CAM结构，使数据访问最小化并匹配比较延迟。 每个比较匹配线和数据位线具有与简单的二维静态随机存取存储器（SRAM）单元阵列相关联的长度。

公开(公告)号：US20120326333A1

公开(公告)日：2012-12-27

申请号：US13607680

申请日：2012-09-08

申请人： Kerry Bernstein ,  Philip G. Emma ,  Michael Ignatowski

发明人： Kerry Bernstein ,  Philip G. Emma ,  Michael Ignatowski

IPC分类号： H01L25/00

CPC分类号： H01L25/0657 ,  H01L25/0652 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A stacked semiconductor chip comprising multiple unit chips contains multiple instances of a first chip component that have a low yield and are distributed among the multiple unit chips. An instance of the first chip component within a first unit chip is logically paired with at least another instance of the first chip component within at least another unit chip so that the combination of the multiple instances of the first chip component across the multiple unit chips constitute a functional block providing the functionality of a fully functional instance of the first chip component. The stacked semiconductor chip may include multiple instances of a second chip component having a high yield and distributed across the multiple unit chips. Multiple low yield components constitute a functional block providing an enhanced overall yield, while high yield components are utilized to their full potential functionality.

摘要翻译： 包括多个单元芯片的堆叠半导体芯片包含具有低产出并分布在多个单元芯片之间的第一芯片组件的多个实例。 第一单元芯片内的第一芯片组件的实例与至少另一个单元芯片内的第一芯片组件的至少另一个实例进行逻辑配对，使得跨多个单元芯片的第一芯片组件的多个实例的组合构成 提供第一芯片组件的完全功能实例的功能的功能块。 层叠的半导体芯片可以包括具有高产量并分布在多个单元芯片上的第二芯片组件的多个实例。 多个低产量组分构成提供增强的总收率的功能块，而高产量组分被用于其全部潜在功能。