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123 条记录 (耗时 0.032 秒)

    Systems and methods for preventing data remanence in memory systems
    51.
    发明授权
    Systems and methods for preventing data remanence in memory systems 有权

    公开(公告)号：US09646177B2

    公开(公告)日：2017-05-09

    申请号：US13098012

    申请日：2011-04-29

    申请人： Bruce B. Pedersen ,  Dirk A. Reese

    发明人： Bruce B. Pedersen ,  Dirk A. Reese

    IPC分类号： G06F7/38 ,  G06F21/79 ,  G06F21/76 ,  G11C7/20 ,  G11C11/419

    CPC分类号： G06F21/79 ,  G06F21/76 ,  G11C7/20 ,  G11C11/419

    摘要： Methods, circuits, and systems for preventing data remanence in memory systems are provided. Original data is stored in a first memory, which may be a static random access memory (SRAM). Data is additionally stored in a second memory. Data in the first memory is periodically inverted, preventing data remanence in the first memory. The data in the second memory is periodically inverted concurrently with the data in the first memory. The data in the second memory is used to keep track of the inversion state of the data in the first memory. The original data in the first memory can be reconstructed performing a logical exclusive-OR operation between the data in the first memory and the data in the second memory.

    Programmable logic device with improved security
    52.
    发明授权
    Programmable logic device with improved security 有权
    可编程逻辑器件具有改进的安全性

    公开(公告)号：US08812869B1

    公开(公告)日：2014-08-19

    申请号：US13557005

    申请日：2012-07-24

    申请人： Bruce B. Pedersen

    发明人： Bruce B. Pedersen

    IPC分类号： G06F11/30 ,  G06F21/76

    CPC分类号： G06F21/76 ,  G06F21/75

    摘要： Techniques of the present invention impede power consumption measurements of an encryption engine on a logic device by running the encryption engine with an independent clock. This clock produces a signal that is decoupled from and asynchronous to clock signals feeding other circuits on the device. The clock feeding the encryption engine is not accessible externally to the device. Circuits may be employed to intentionally slow down or add jitter to one or more of the clock signals.

    摘要翻译： 本发明的技术通过运行具有独立时钟的加密引擎来阻碍逻辑设备上的加密引擎的功耗测量。 该时钟产生与馈送设备上的其他电路的时钟信号去耦和异步的信号。 馈送加密引擎的时钟不能从设备外部访问。 可以采用电路有意地将抖动减慢或增加到一个或多个时钟信号。

    Reconfigurable logic block
    54.
    发明授权
    Reconfigurable logic block 有权

    公开(公告)号：US08572538B2

    公开(公告)日：2013-10-29

    申请号：US13369226

    申请日：2012-02-08

    申请人： David W. Mendel ,  Gary Lai ,  Lu Zhou ,  Bruce B. Pedersen

    发明人： David W. Mendel ,  Gary Lai ,  Lu Zhou ,  Bruce B. Pedersen

    IPC分类号： G06F17/50 ,  H03K19/173

    CPC分类号： G06F17/5054 ,  G06F11/1008 ,  H03K19/17756 ,  H03K19/17776

    摘要： A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors.

    Specifying placement and routing constraints for security and redundancy
    55.
    发明授权
    Specifying placement and routing constraints for security and redundancy 有权
    指定安全和冗余的布局和路由约束

    公开(公告)号：US08434044B1

    公开(公告)日：2013-04-30

    申请号：US12968128

    申请日：2010-12-14

    申请人： David Samuel Goldman ,  Bruce B. Pedersen ,  Gabriel Quan ,  Yuen Ho Choi

    发明人： David Samuel Goldman ,  Bruce B. Pedersen ,  Gabriel Quan ,  Yuen Ho Choi

    IPC分类号： G06F17/50 ,  G06F13/14

    CPC分类号： G06F17/5072

    摘要： A programmable chip design tool is provided to enumerate and specify the security and/or redundancy constraints of a programmable chip design. A design is implemented with a high-level security or redundancy scheme, and the programmable chip design tool applies the scheme while simultaneously optimizing for desired metrics (logic density, routability, timing, power, etc.). An underlying assignment scheme as well as user interface components used to enter this assignment scheme are provided.

    摘要翻译： 提供了一种可编程芯片设计工具来枚举和指定可编程芯片设计的安全和/或冗余约束。 设计采用高级安全或冗余方案实现，而可编程芯片设计工具则应用该方案同时优化所需度量（逻辑密度，可布线性，时序，功率等）。 提供了一个底层分配方案以及用于输入此分配方案的用户界面组件。

    Hardware true random number generator in integrated circuit with tamper detection
    56.
    发明授权
    Hardware true random number generator in integrated circuit with tamper detection 有权
    硬件真实随机数发生器集成电路中的篡改检测

    公开(公告)号：US08321773B1

    公开(公告)日：2012-11-27

    申请号：US12262666

    申请日：2008-10-31

    申请人： Bruce B. Pedersen

    发明人： Bruce B. Pedersen

    IPC分类号： G06F11/00

    CPC分类号： G06F7/588 ,  G06F21/554 ,  G06F21/71 ,  G06F21/86

    摘要： Circuits and methods to generate a True Random Number Generator (TRNG) with tamper-detection are presented. In one embodiment, the circuit includes two identical TRNG circuits and logic circuitry that combines and correlates the outputs of the two TRNG circuits. The two identical TRNG circuits are located in close proximity to each other inside an Integrated Circuit (IC). The logic circuitry analyzes the outputs of the two TRNG circuits and the historical values of the relation between the outputs of the two TRNG circuits to determine if the outputs are correlated. If the outputs are not correlated, the logic circuitry outputs a true random number sequence based on the combination of the two TRNG circuits. As a result, circuit tampering, such as changes in temperature or voltage supplies, is detected in the IC.

    摘要翻译： 介绍了使用篡改检测来生成真随机数发生器（TRNG）的电路和方法。 在一个实施例中，电路包括两个相同的TRNG电路和逻辑电路，其组合和相关两个TRNG电路的输出。 两个相同的TRNG电路位于集成电路（IC）内彼此靠近的位置。 逻辑电路分析两个TRNG电路的输出和两个TRNG电路的输出之间的关系的历史值，以确定输出是否相关。 如果输出不相关，则逻辑电路基于两个TRNG电路的组合输出真正的随机数序列。 结果，在IC中检测到电路篡改，例如温度变化或电压供应。

    Volatile memory elements with soft error upset immunity
    57.
    发明授权
    Volatile memory elements with soft error upset immunity 有权
    易失性记忆元件，具有柔软的错误不耐受性

    公开(公告)号：US07872903B2

    公开(公告)日：2011-01-18

    申请号：US12407762

    申请日：2009-03-19

    申请人： Bruce B. Pedersen

    发明人： Bruce B. Pedersen

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412 ,  G11C7/20 ,  G11C11/4125 ,  H03K19/00392 ,  H03K19/177 ,  H03K19/1776 ,  H03K19/17764

    摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected to form a bistable element. Clear lines such as true and complement clear lines may be routed to positive power supply terminals and ground power supply terminals associated with certain transistor pairs. During clear operations, some or all of the transistor pairs can be selectively depowered using the clear lines. This facilitates clear operations in which logic zero values are driven through the address transistors and reduces cross-bar current surges.

    摘要翻译： 提供了存储元件，当受到高能原子粒子撞击时，表现出对软错误失调事件的抵抗力。 存储元件可以各自具有十个晶体管，其包括互连以形成双稳态元件的两个地址晶体管和四个晶体管对。 诸如真实和补充清除线之类的清除线可以被路由到与某些晶体管对相关联的正电源端子和接地电源端子。 在清除操作期间，可以使用清除线选择性地削弱部分或全部晶体管对。 这有助于明确的操作，其中逻辑零值通过地址晶体管驱动并且减小交叉电流浪涌。

    Transceiver system with reduced latency uncertainty
    58.
    发明申请
    Transceiver system with reduced latency uncertainty 有权
    收发器系统具有降低的延迟不确定性

    公开(公告)号：US20090161738A1

    公开(公告)日：2009-06-25

    申请号：US12283652

    申请日：2008-09-15

    申请人： Neville Carvalho ,  Allan Thomas Davidson ,  Andy Turudic ,  Bruce B. Pedersen ,  David W. Mendel ,  Kalyan Kankipati ,  Michael Menghui Zheng ,  Sergey Shumarayev ,  Seungmyon Park ,  Tim Tri Hoang ,  Kumara Tharmalingam

    发明人： Neville Carvalho ,  Allan Thomas Davidson ,  Andy Turudic ,  Bruce B. Pedersen ,  David W. Mendel ,  Kalyan Kankipati ,  Michael Menghui Zheng ,  Sergey Shumarayev ,  Seungmyon Park ,  Tim Tri Hoang ,  Kumara Tharmalingam

    IPC分类号： H04L7/00 ,  H04B1/38

    CPC分类号： H04L25/14

    摘要： A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.

    摘要翻译： 描述了具有降低的等待时间不确定性的收发机系统。 在一个实现中，收发器系统具有字对齐器等待时间不确定度为零。 在另一个实现中，收发器系统具有接收器到发射器的传输等待时间不确定度为零。 在另一个实现中，收发器系统具有字对齐器延迟不确定度为零和接收器到发射器的传输等待时间不确定度为零。 在一个具体实现中，通过在发射机锁相环（PLL）中使用发射机并行时钟作为反馈信号来消除接收机到发射机的传输等待时间不确定性。 在一个实现中，这通过可选地使发射机分频器（其产生发射机并行时钟）作为发射机PLL的反馈路径的一部分来实现。 在一个实施方案中，通过使用位拖动器以这样的方式滑动位来消除字对齐器延迟不确定性，使得由于字对齐和位滑动引起的总延迟对于恢复时钟的所有阶段是恒定的。 这允许在由解串器的并行化的所有阶段的位的接收和传输之间具有固定和已知的等待时间。 在一个具体实现中，由于位对准器的位移和由位拖动器的位滑动导致的总延迟为零，因为位拖动器滑动位，以补偿由字对准器执行的位移。