公开(公告)号：US06498104B1

公开(公告)日：2002-12-24

申请号：US09776308

申请日：2001-02-02

申请人： Fuodoor Gologhlan ,  David Chi ,  Kent Kuohua Chang ,  Hector Serrato

发明人： Fuodoor Gologhlan ,  David Chi ,  Kent Kuohua Chang ,  Hector Serrato

IPC分类号： H01L21311

CPC分类号： C23C16/4412 ,  C23C16/4405 ,  C23C16/4407

摘要： In one embodiment, the present invention relates to a method of cleaning a low pressure chemical vapor deposition apparatus having TEOS material build-up therein involving contacting the low pressure chemical vapor deposition apparatus with a composition containing at least one lower alcohol. In another embodiment, the present invention relates to a system for cleaning a low pressure chemical vapor deposition apparatus having TEOS material build-up therein, containing a supply of a composition comprising at least one lower alcohol; an injection port for introducing the composition including at least one lower alcohol into the low pressure chemical vapor deposition apparatus; and a pump/vacuum system for removing crystallized TEOS material build-up from the low pressure chemical vapor deposition apparatus.

摘要翻译： 在一个实施方案中，本发明涉及清洗其中包含TEOS材料的低压化学气相沉积设备的方法，其中包括使低压化学气相沉积设备与含有至少一种低级醇的组合物接触。 在另一个实施方案中，本发明涉及用于清洗其中含有TEOS材料的低压化学气相沉积设备的系统，其中含有至少一种低级醇的组合物; 用于将包含至少一种低级醇的组合物引入低压化学气相沉积装置的注入口; 以及用于从低压化学气相沉积装置中除去结晶的TEOS材料积聚的泵/真空系统。

公开(公告)号：US06487114B2

公开(公告)日：2002-11-26

申请号：US09795937

申请日：2001-02-28

申请人： Fuh-Cheng Jong ,  Kent Kuohua Chang

发明人： Fuh-Cheng Jong ,  Kent Kuohua Chang

IPC分类号： G11C1604

CPC分类号： G11C16/26 ,  G11C16/0475

摘要： A method of reading two-bit information in Nitride Read only memory (NROM) cell simultaneously. According to outputted voltage in drain or source of the NROM, it can identify a logical two-bit combination massage of the NROM. The method includes: grounding the source of the NROM; inputting a voltage to the drain of the NROM; inputting a voltage to the gate of the NROM; measuring the outputted current of drain or source; and dividing the outputted current into four different zones, and each zone represents a specific logical two-bit information, which is “0 and 0”, “0 and 1”, “1 and 0”, or “1 and 1”.

公开(公告)号：US06458212B1

公开(公告)日：2002-10-01

申请号：US09539393

申请日：2000-03-31

申请人： Fuodoor Gologhlan ,  David Chi ,  Kent Kuohua Chang ,  Hector Serrato ,  Jayendra Bhakta

发明人： Fuodoor Gologhlan ,  David Chi ,  Kent Kuohua Chang ,  Hector Serrato ,  Jayendra Bhakta

IPC分类号： C23C1600

CPC分类号： C23C16/4412 ,  Y10S55/30

摘要： One aspect of the present invention relates to a tetraethylorthosilicate chemical vapor deposition method, involving the steps of forming a film on a substrate using tetraethylorthosilicate in a chemical vapor deposition chamber; and removing tetraethylorthosilicate byproducts from the chemical vapor deposition chamber via a pump system and an exhaust line connected to the chemical vapor deposition chamber, the exhaust line comprising a mesh filter having a conical shape. Another aspect of the present invention relates to an exhaust system for removing tetraethylorthosilicate byproducts from a chemical vapor deposition chamber, containing an exhaust line connected to the chemical vapor deposition chamber, the exhaust line comprising a mesh filter having a conical shape via a pump system; and a pump system connected to the exhaust line for removing tetraethylorthosilicate byproducts from the processing chamber.

摘要翻译： 本发明的一个方面涉及一种四乙基原硅酸盐化学气相沉积方法，包括以下步骤：在化学气相沉积室中使用原硅酸四乙酯在基底上形成膜; 以及经由泵系统和连接到化学气相沉积室的排气管线从化学气相沉积室除去原硅酸四乙酯副产物，排气管线包括具有圆锥形状的网状过滤器。 本发明的另一方面涉及一种用于从化学气相沉积室除去原硅酸四乙酯副产物的排气系统，该排气系统包含连接到化学气相沉积室的排气管线，该排气管线包括经由泵系统具有锥形形状的网状过滤器; 以及与排气管连接以从处理室除去原硅酸四乙酯副产物的泵系统。

公开(公告)号：US06420237B1

公开(公告)日：2002-07-16

申请号：US09682809

申请日：2001-10-22

申请人： Kent Kuohua Chang

发明人： Kent Kuohua Chang

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  G11C11/5621 ,  G11C16/0458 ,  H01L27/115 ,  H01L29/7887

摘要： The present invention provides a twin bit cell flash memory device and its fabricating method. The method is to first form a gate oxide layer on the surface of the silicon substrate followed by forming a polysilicon germanium (Si1−xGex,x=0.05˜1.0) layer on the gate oxide layer. Thereafter, an ion implantation process is performed to form at least one insulating region in the polysilicon germanium layer for separating the polysilicon germanium layer into two isolated conductive regions and forming a twin bit cell structure. Then, a dielectric layer is formed on the polysilicon germanium layer and a photo-etching-process (PEP) is performed to etch portions of the dielectric layer and the polysilicon germanium layer for forming a floating gate of the twin bit cell flash memory. Finally, a control gate is formed over the floating gate.

摘要翻译： 本发明提供一种双位单元闪存器件及其制造方法。 该方法首先在硅衬底的表面上形成栅氧化层，然后在栅极氧化层上形成多晶锗（Si1-xGex，x = 0.05〜1.0）层。 此后，进行离子注入工艺以在多晶硅锗层中形成至少一个绝缘区域，用于将多晶硅锗层分离成两个隔离的导电区域并形成双位晶胞结构。 然后，在多晶硅锗层上形成电介质层，并进行光蚀刻工艺（PEP）以蚀刻介电层和多晶硅锗层的部分，以形成双位晶胞闪存的浮动栅极。 最后，在浮动栅极上形成控制栅极。

公开(公告)号：US06376309B2

公开(公告)日：2002-04-23

申请号：US09811288

申请日：2001-03-16

申请人： John JianShi Wang ,  Kent Kuohua Chang ,  Hao Fang ,  Lu You

发明人： John JianShi Wang ,  Kent Kuohua Chang ,  Hao Fang ,  Lu You

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L21/76837 ,  H01L27/115

摘要： The present invention provides a method for reducing the gate aspect ratio of a flash memory device. The method includes forming a tunnel oxide layer on a substrate; forming a polysilicon layer on the tunnel oxide layer; forming an insulating layer on the polysilicon layer; forming a control gate layer on the polysilicon layer; etching at least the tunnel oxide layer, the insulating layer, and the control gate layer to form at least two stack structures; forming a plurality of spacers at sides of the at least two stack structures; and filling at least one gap between the at least two stack structures with an oxide, where the control gate layer provides a gate aspect ratio which allows for a maximum step coverage by the oxide. In a preferred embodiment, the method uses nickel silicide instead of the conventional tungsten silicide in the control gate layers of the cells of the device. Nickel silicide has higher conductivity than conventional silicides, thus a thinner layer of nickel silicide may be used without sacrificing performance. Nickel silicide also has a lower barrier height for holes, thus maintaining a low contact resistance. With a thinner nickel silicide layer, the gate aspect ratio of the cells are lowered, allowing for a maximum step coverage by the gap-filling oxide. The reliability of the device is thus improved.

摘要翻译： 本发明提供一种降低闪速存储器件的栅极纵横比的方法。 该方法包括在衬底上形成隧道氧化物层; 在隧道氧化层上形成多晶硅层; 在所述多晶硅层上形成绝缘层; 在所述多晶硅层上形成控制栅极层; 至少蚀刻隧道氧化物层，绝缘层和控制栅极层以形成至少两个堆叠结构; 在所述至少两个堆叠结构的侧面处形成多个间隔物; 以及用所述氧化物填充所述至少两个堆叠结构之间的至少一个间隙，其中所述控制栅极层提供允许所述氧化物的最大阶跃覆盖的栅极纵横比。 在优选实施例中，该方法在装置的电池的控制栅极层中使用硅化镍代替常规的硅化钨。 硅化镍具有比常规硅化物更高的导电性，因此可以使用更薄的硅化镍层而不牺牲性能。 硅化镍也具有较低的孔的阻挡高度，因此保持低的接触电阻。 利用更薄的硅化镍层，电池的栅极纵横比降低，允许通过间隙填充氧化物的最大阶梯覆盖。 因此提高了装置的可靠性。

公开(公告)号：US06362049B1

公开(公告)日：2002-03-26

申请号：US09435213

申请日：1999-11-05

申请人： Salvatore F. Cagnina ,  Hao Fang ,  John Jianshi Wang ,  Kent Kuohua Chang ,  Masaatzi Higashitani

发明人： Salvatore F. Cagnina ,  Hao Fang ,  John Jianshi Wang ,  Kent Kuohua Chang ,  Masaatzi Higashitani

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/11546

摘要： A semiconductor process for fabricating NAND type flash memory devices in a first embodiment includes step which can be performed on a production line which manufactures NOR type flash memory products. A NAND flash memory fabrication process according to a second embodiment simplifies the process and uses fewer masks, thus reducing costs and errors to produce higher yields.

摘要翻译： 在第一实施例中用于制造NAND型闪速存储器件的半导体工艺包括可以在制造NOR型闪存产品的生产线上执行的步骤。 根据第二实施例的NAND闪存制造工艺简化了处理并且使用较少的掩模，从而降低成本和错误以产生更高的产量。

公开(公告)号：US06184084B2

公开(公告)日：2001-02-06

申请号：US09263701

申请日：1999-03-05

申请人： David Chi ,  Kent Kuohua Chang ,  Yuesong He

发明人： David Chi ,  Kent Kuohua Chang ,  Yuesong He

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/3212

摘要： In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer; forming a second polysilicon layer over the insulating layer by depositing an second polysilicon layer having a first thickness, and then using chemical mechanical polishing to form a second polysilicon layer having a second thickness, wherein the second thickness is at least about 25% less than the first thickness; forming a tungsten silicide layer over the second polysilicon layer by chemical vapor deposition using WF6 and SiH4; etching at least the first polysilicon layer, the second polysilicon layer, the insulating layer, and the tungsten silicide layer thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.

摘要翻译： 在一个实施例中，本发明涉及一种形成闪速存储器单元的方法，包括在衬底上形成隧道氧化物的步骤; 在隧道氧化物上形成第一多晶硅层; 在所述第一多晶硅层上形成绝缘层; 通过沉积具有第一厚度的第二多晶硅层，然后使用化学机械抛光形成具有第二厚度的第二多晶硅层，在所述绝缘层上形成第二多晶硅层，其中所述第二厚度比所述第二厚度小至少约25％ 第一厚度 通过使用WF6和SiH4的化学气相沉积在第二多晶硅层上形成硅化钨层; 至少蚀刻第一多晶硅层，第二多晶硅层，绝缘层和硅化钨层，从而限定至少一个堆叠栅极结构; 以及在衬底中形成源区和漏区，由此形成至少一个存储单元。

公开(公告)号：US06177312B1

公开(公告)日：2001-01-23

申请号：US09048459

申请日：1998-03-26

申请人： Yuesong He ,  John Jianshi Wang ,  Toru Ishigaki ,  Kent Kuohua Chang ,  Effiong Ibok

发明人： Yuesong He ,  John Jianshi Wang ,  Toru Ishigaki ,  Kent Kuohua Chang ,  Effiong Ibok

IPC分类号： H01L2128

CPC分类号： H01L21/28211 ,  H01L21/31116 ,  H01L21/3185 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11536 ,  Y10S438/974

摘要： This invention relates to a method for removing contaminate nitrogen from the peripheral gate region of a non-volatile memory device during production of said device, wherein at least some of the contaminate nitrogen has formed a bond with the surface of the silicon substrate in contact with the gate oxide layer in said gate region, said method comprising: contacting said gate oxide layer and contaminate nitrogen with a gas comprising ozone at a temperature of about 850° C. to about 950° C. for an effective period of time to break said bond; and removing said gate oxide layer and contaminate nitrogen from said surface of said silicon substrate.

摘要翻译： 本发明涉及一种在制造所述装置期间从非易失性存储装置的外围栅极区域去除污染氮的方法，其中至少一些污染氮已经与硅衬底的表面形成了接触， 所述栅极区域中的栅极氧化物层，所述方法包括：使接触所述栅极氧化物层并且在约850℃至约950℃的温度下将含有包含臭氧的气体氮气与有毒时间隔离以破坏所述 键; 以及去除所述栅极氧化物层并从所述硅衬底的所述表面污染氮。

公开(公告)号：US5981339A

公开(公告)日：1999-11-09

申请号：US45013

申请日：1998-03-20

申请人： Kent Kuohua Chang ,  David Chi ,  Yuesong He

发明人： Kent Kuohua Chang ,  David Chi ,  Yuesong He

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8247

CPC分类号： H01L21/28202 ,  H01L21/28211 ,  H01L29/4916 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66825

摘要： In one embodiment, the present invention relates to a method of forming a flash memory cell involving the steps of: forming a tunnel oxide on a substrate; forming an in situ phosphorus doped polysilicon layer over the tunnel oxide by low pressure chemical vapor deposition at a temperature between about 610.degree. C. and about 630.degree. C., wherein the in situ phosphorus doped polysilicon layer comprises from about 1.times.10.sup.19 atoms/cm.sup.3 to about 5.times.10.sup.19 atoms/cm.sup.3 of phosphorus; forming an insulating layer over the in situ phosphorus doped polysilicon layer; forming a conductive layer over the insulating layer; etching the in situ phosphorus doped polysilicon layer, the conductive layer and the insulating layer, thereby defining one or more stacked gate structures; and forming a source region and a drain region in the substrate, wherein the source region and the drain region are self-aligned by the stacked gate structures, thereby forming one or more memory cells.

摘要翻译： 在一个实施例中，本发明涉及一种形成闪存单元的方法，该方法包括以下步骤：在衬底上形成隧道氧化物; 在约610℃至约630℃的温度下通过低压化学气相沉积在隧道氧化物上形成原位磷掺杂多晶硅层，其中原位磷掺杂多晶硅层包含约1×1019原子/ cm3至 约5×1019原子/ cm3磷; 在原位磷掺杂多晶硅层上形成绝缘层; 在所述绝缘层上形成导电层; 蚀刻原位磷掺杂多晶硅层，导电层和绝缘层，从而限定一个或多个堆叠栅极结构; 以及在所述衬底中形成源区和漏区，其中所述源极区和所述漏区由所述堆叠栅极结构自对准，从而形成一个或多个存储单元。

公开(公告)号：US20140080096A1

公开(公告)日：2014-03-20

申请号：US14055718

申请日：2013-10-16

申请人： Kent Kuohua Chang

发明人： Chao-Fu Chang ,  Kent Kuohua Chang

IPC分类号： A61C8/02

CPC分类号： A61C8/0006 ,  A61L31/088 ,  A61L31/146 ,  A61L2400/12

摘要： A guided tissue regeneration membrane has a top surface, a bottom surface and the two surfaces are characterized by the plurality of through conical holes. Each of the plurality of through holes has a base opening on the top surface and a tip opening on the bottom surface. The diameter of the base opening is larger than that of the tip opening The guided tissue regeneration membrane is placed between a hard tissue and a soft tissue of gums with the top surface thereof facing the hard tissue so as to hinder the soft tissue from rapidly growing. The tip openings are available for the soft tissue to supply nutrient to the hard tissue therethrough. The hard tissue can grow from the base openings, through the corresponding through holes and to the soft tissue to repair periodontal tissue. In order to achieve a better affinity for cell growth, the guided tissue membrane surface facing the bony surface is coated with a hydrophilic, bioactive and biocompatible nano scaled oxidation layer.

摘要翻译： 引导组织再生膜具有顶表面，底表面，两个表面的特征在于多个通孔。 多个通孔中的每一个在顶表面上具有基部开口，在底面上具有顶端开口。 基部开口的直径大于尖端开口的直径引导的组织再生膜被放置在硬组织和牙龈的软组织之间，其顶表面面向硬组织，从而阻碍软组织快速生长 。 尖端开口可用于软组织，以通过其中的硬组织提供营养。 硬组织可以从基底开口，通过相应的通孔和软组织生长，以修复牙周组织。 为了实现对细胞生长的更好的亲和力，面向骨表面的引导组织膜表面涂覆有亲水的，生物活性的和生物相容的纳米级氧化层。