Integrated circuit
    51.
    发明申请
    Integrated circuit 有权
    集成电路

    公开(公告)号:US20060267681A1

    公开(公告)日:2006-11-30

    申请号:US11138671

    申请日:2005-05-27

    申请人: Michael Sommer

    发明人: Michael Sommer

    IPC分类号: G05B7/02

    CPC分类号: G11C7/1078 G11C7/1084

    摘要: An integrated circuit includes a first and a second amplifier circuit each driven by an input signal. The first and second amplifier circuits generate a first and a second control signal on the output side. The control signals are generated independently of one another and drive a first and second controllable resistor of a third amplifier circuit for generating a third control signal. The third control signal is fed back to the first and second amplifier circuits. Depending on the resistance value of the first and second controllable resistors of the third amplifier circuit, an output signal amplified with respect to the input signal is generated at an output terminal of the integrated circuit. The integrated circuit is an input amplifier of an integrated semiconductor memory and permits the input signal to be amplified with a gain independent of a level of the DC component of the input signal.

    摘要翻译: 集成电路包括由输入信号驱动的第一和第二放大器电路。 第一和第二放大器电路在输出侧产生第一和第二控制信号。 控制信号彼此独立地产生,并且驱动第三放大器电路的第一和第二可控电阻器,以产生第三控制信号。 第三控制信号被反馈到第一和第二放大器电路。 根据第三放大器电路的第一和第二可控电阻的电阻值,在集成电路的输出端产生相对于输入信号放大的输出信号。 集成电路是集成半导体存储器的输入放大器,并允许以与输入信号的DC分量的电平无关的增益放大输入信号。

    Integrated semiconductor memory
    52.
    发明申请
    Integrated semiconductor memory 审中-公开
    集成半导体存储器

    公开(公告)号:US20060187728A1

    公开(公告)日:2006-08-24

    申请号:US11238625

    申请日:2005-09-29

    IPC分类号: G11C7/00

    摘要: An integrated semiconductor memory (100) comprises a controllable voltage generator (30) for precharging bit lines (BL) of a memory cell array (10) to a precharge voltage (VEQ). During the read-out of a first and second memory state of memory cells (SZ) which are connected to the bit lines, a first and second signal swing (ΔUH, ΔUL) occurs on the bit lines, as a result of which the bit lines are charged to a first and a second voltage potential (V1, V2). For the purpose of precharging the bit lines to the precharge voltage (VEQ), a first equalize current (I1) and a second equalize current (I2) are fed onto the bit lines by the controllable voltage generator (30), the current intensity of said currents in each case being measured by a detector circuit (60). A control circuit (20) alters the precharge voltage (VEQ) until the first and second equalize currents (I1, I2) have identical magnitudes. The precharge voltage is then centered with respect to the first and second voltage potentials (V1, V2).

    摘要翻译: 集成半导体存储器(100)包括用于将存储单元阵列(10)的位线(BL)预充电到预充电电压(VEQ)的可控电压发生器(30)。 在连接到位线的存储单元(SZ)的第一和第二存储器状态的读出期间,在位线上出现第一和第二信号摆幅(DeltaUH,DeltaUL),结果是位 线路被充电到第一和第二电压电位(V 1,V 2)。 为了将位线预充电到预充电电压(VEQ),通过可控电压发生器(30)将第一均衡电流(I 1)和第二均衡电流(I 2)馈送到位线,电流 每种情况下所述电流的强度由检测器电路(60)测量。 控制电路(20)改变预充电电压(VEQ),直到第一和第二均衡电流(I 1,I 2)具有相同的幅度。 然后,预充电电压相对于第一和第二电压电位(V 1,V 2)居中。

    Method for elimination of false reactivities in immunoassay for Hepatitis A virus
    53.
    发明申请
    Method for elimination of false reactivities in immunoassay for Hepatitis A virus 审中-公开
    在甲型肝炎病毒免疫测定中消除假反应性的方法

    公开(公告)号:US20060134647A1

    公开(公告)日:2006-06-22

    申请号:US11016224

    申请日:2004-12-17

    IPC分类号: C12Q1/68 G01N33/53

    CPC分类号: G01N33/5768 Y02A50/54

    摘要: An ancillary reducing reagent composition is used to significantly reduce and substantially eliminate the incidence of false positive results in an immunoassay for the detection of antibodies to Hepatitis A virus. The reducing agent contained in the ancillary reducing reagent composition is a sulfhydryl compound buffered to a pH sufficient to prevent oxidation of the reducing agent.

    摘要翻译: 辅助还原剂组合物用于显着减少并基本上消除用于检测甲型肝炎病毒抗体的免疫测定中的假阳性结果的发生率。 辅助还原剂组合物中所含的还原剂是缓冲至足以防止还原剂氧化的pH的巯基化合物。

    Method for producing a TFA image sensor and one such TFA image sensor
    54.
    发明申请
    Method for producing a TFA image sensor and one such TFA image sensor 有权
    用于生产TFA图像传感器和一个这样的TFA图像传感器的方法

    公开(公告)号:US20060102829A1

    公开(公告)日:2006-05-18

    申请号:US11271492

    申请日:2005-11-11

    IPC分类号: H01L27/00 H01L31/00

    摘要: The invention relates to a method for producing a TFA image sensor in which a multi-layer arrangement comprising a photo diode matrix is arranged on an ASIC switching circuit provided with electronic circuits for operating the TFA image sensor, such as pixel electronics, peripheral electronics and system electronics, for the pixel-wise conversion of electromagnetic radiation into an intensity-dependent photocurrent, the pixels being connected to contacts of the underlying pixel electronics of the ASIC switching circuit. The method enables conventionally produced ASIC switching circuits to be used without impairing the topography of the photoactive sensor surface. The CMOS passivation layer in the photoactive region and then the upper CMOS metallization are removed and replaced by a metallic layer which is structured in the pixel raster, for the formation of back electrodes. The photo diode matrix is then applied and structured, said photo diode matrix being embodied as a pixel matrix, on which a passivating protective layer and/or a color filter layer having a passivating action can be applied.

    摘要翻译: 本发明涉及一种制造TFA图像传感器的方法,其中包括光电二极管阵列的多层布置被布置在ASIC切换电路上,该ASIC开关电路设置有用于操作TFA图像传感器的电子电路,例如像素电子器件,外围电子器件和 系统电子器件,用于将电磁辐射像素地转换成强度依赖的光电流,像素连接到ASIC开关电路的底层像素电子器件的触点。 该方法能够在不损害光敏传感器表面的形貌的情况下使用常规生产的ASIC切换电路。 去除光致活性区域中的CMOS钝化层,然后去除上部CMOS金属化的CMOS钝化层,并由构成像素栅格的金属层代替以形成背面电极。 然后施加和构造光电二极管矩阵,所述光电二极管矩阵被实现为像素矩阵,其上可以应用具有钝化作用的钝化保护层和/或滤色器层。

    DRAM memory cell and memory cell array with fast read/write access
    55.
    发明授权
    DRAM memory cell and memory cell array with fast read/write access 失效
    DRAM存储单元和具有快速读/写访问的存储单元阵列

    公开(公告)号:US06979853B2

    公开(公告)日:2005-12-27

    申请号:US10462533

    申请日:2003-06-16

    摘要: The memory cell according to the invention has a vertical selection transistor, via whose channel region the inner electrode of the trench capacitor can be connected to a bit line. The large extent of the channel region in the bit line direction means that the trench capacitor can be rapidly charged and read. The channel region is led to the bit line through an associated word line, which completely or partially encloses the channel region. A conductive channel can be formed within the channel region depending on the potential of the word line.

    摘要翻译: 根据本发明的存储单元具有垂直选择晶体管,其通道区域可以将沟槽电容器的内部电极连接到位线。 位线方向上的沟道区域的大范围意味着沟槽电容器可以被快速充电和读取。 通道区域通过相关联的字线被引导到位线,该字线完全或部分地包围通道区域。 取决于字线的电位,可以在通道区域内形成导电沟道。

    Input circuit for an electronic circuit and a method for controlling the reading-in of a data signal
    56.
    发明申请
    Input circuit for an electronic circuit and a method for controlling the reading-in of a data signal 有权
    电子电路的输入电路和控制数据信号读入的方法

    公开(公告)号:US20050225357A1

    公开(公告)日:2005-10-13

    申请号:US11087976

    申请日:2005-03-22

    摘要: The invention relates to a method for controlling the reading-in of a data signal at an input of an electrical circuit to an input latch with the aid of a clock signal, with the data item, which is indicated by the data signal, being transferred to the input latch with a clock edge of the clock signal, with the clock edge of the clock signal being shifted in time as a function of a time delay between a signal edge of the input signal at the input and the clock edge, such that the time delay between the signal edge of the data signal and the clock edge is within a predetermined time window.

    摘要翻译: 本发明涉及一种用于通过时钟信号控制在电路输入到输入锁存器的数据信号的读入的方法,由数据信号指示的数据项被传送 与时钟信号的时钟沿一起输入到具有时钟信号的时钟边沿的输入锁存器,其中时钟信号的时钟沿时间沿着输入端的输入信号的信号边沿与时钟沿之间的时间延迟的时间偏移,使得 数据信号的信号边沿与时钟边沿之间的时间延迟在预定时间窗内。

    Integrated circuit with voltage divider and buffered capacitor
    57.
    发明授权
    Integrated circuit with voltage divider and buffered capacitor 有权
    集成电路与分压器和缓冲电容器

    公开(公告)号:US06930540B2

    公开(公告)日:2005-08-16

    申请号:US10460714

    申请日:2003-06-12

    IPC分类号: G11C5/14 G11C11/4074 G05F3/02

    摘要: An integrated circuit has a voltage divider that is configured to save current. The circuit includes a capacitor that is inventively connected to a potential sink or potential source by way of a charge branch even when the voltage divider is inactive. The capacitor is thus held at a charge state that corresponds to the charge state given an active voltage divider. The voltage divider thus becomes functional in a shorter time following activation, because the capacitor does not require recharging.

    摘要翻译: 集成电路具有配置为节省电流的分压器。 电路包括电容器,即使当分压器不活动时,电容器通过电荷分支发明地连接到电位吸收器或电位源。 因此,电容器保持在对应于给定有源分压器的充电状态的充电状态。 因此,由于电容器不需要充电,因此分压器在激活后的较短时间内变得功能化。

    Integrated semiconductor memory circuit and method of manufacturing the same
    59.
    发明申请
    Integrated semiconductor memory circuit and method of manufacturing the same 失效
    集成半导体存储器电路及其制造方法

    公开(公告)号:US20050029602A1

    公开(公告)日:2005-02-10

    申请号:US10753407

    申请日:2004-01-09

    申请人: Michael Sommer

    发明人: Michael Sommer

    摘要: An integrated semiconductor circuit, having active components lying in mutually adjoining wells of a respective first and second conduction type, wherein the active components respectively are associated with substrate contacts lying in direct proximity to an edge bounding the mutually adjoining wells, is disclosed. Preferably, structures of the active components other than the contacts are arranged to lie further away from the edge and the circuit/layout structures are not mirror-symmetrical with respect to a center line of the circuit chip.

    摘要翻译: 公开了一种集成半导体电路,其具有位于相应的第一和第二导电类型的相互邻接的阱中的有源部件,其中所述有源部件分别与位于邻近所述相互邻接的阱的边缘直接接近的衬底接触相关联。 优选地,除了触点之外的有源部件的结构布置成更远离边缘,并且电路/布局结构相对于电路芯片的中心线不是镜像对称的。

    Reagent composition for the analysis of residual white blood cells in leuko-reduced blood banking products
    60.
    发明申请
    Reagent composition for the analysis of residual white blood cells in leuko-reduced blood banking products 有权
    用于分析白血病减少血库产品中残留白细胞的试剂组合物

    公开(公告)号:US20050026240A1

    公开(公告)日:2005-02-03

    申请号:US10896338

    申请日:2004-07-21

    摘要: The enumeration and analysis of residual white blood cells in a sample of leukocyte-reduced blood products is conducted by forming a suspension of the leukocyte-reduced blood products with a sufficient amount of a lysing reagent. The lysing reagent comprises a buffer with a low molar concentration, and a non-ionic surfactant. The suspension of leukocyte-reduced blood products and the lysing reagent is incubated for a sufficient time at a temperature sufficient to selectively lyse the platelets and red blood cells without damaging the white blood cells. The white blood cells of the lysed blood products are then contacted with a suitable dye to stain the white blood cells and the number of stained white blood cells is measured. The lysing reagent is free of harsh organic solvents which can damage the plastic components of automated clinical analyzers.

    摘要翻译: 通过用足够量的裂解试剂形成白细胞减少的血液制品的悬浮液来进行白细胞减少的血液制品样品中的残余白细胞的计数和分析。 裂解试剂包含具有低摩尔浓度的缓冲液和非离子表面活性剂。 将白细胞减少的血液制品和裂解试剂的悬浮液在足以在不损伤白细胞的情况下足以选择性地裂解血小板和红细胞的温度下孵育足够的时间。 然后将裂解的血液制品的白细胞与合适的染料接触以染色白细胞,并测量染色的白细胞数。 裂解试剂不含苛刻的有机溶剂,可能会损坏自动化临床分析仪的塑料部件。