公开(公告)号：US07537968B2

公开(公告)日：2009-05-26

申请号：US11765254

申请日：2007-06-19

申请人： S. Brad Herner

发明人： S. Brad Herner

IPC分类号： H01L21/82

CPC分类号： H01L29/861 ,  G11C17/16 ,  G11C17/165 ,  G11C2213/33 ,  G11C2213/71 ,  G11C2213/72 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02667 ,  H01L27/1021 ,  H01L29/161 ,  H01L29/66136

摘要： A method for annealing a diode formed of a silicon-germanium alloy that minimizes leakage current is disclosed. The method includes the steps of forming semiconductor pillars of an alloy of silicon and germanium; heating the pillars at a first temperature for at least 30 minutes, and then heating the pillars at a second temperature higher than the first temperature of the alloy for up to 120 seconds. The invention further includes a monolithic three dimensional memory array of a plurality of p-i-n diodes, the p-i-n diodes being formed of a silicon-germanium alloy that have been subjected to a two-stage heating process.

摘要翻译： 公开了一种使由硅 - 锗合金形成的二极管退火的方法，其使泄漏电流最小化。 该方法包括形成硅和锗的合金的半导体柱的步骤; 在第一温度下加热柱子至少30分钟，然后在高于合金的第一温度的第二温度下加热柱子长达120秒。 本发明还包括多个p-i-n二极管的单片三维存储器阵列，p-i-n二极管由已进行两级加热处理的硅 - 锗合金形成。

公开(公告)号：US20080316808A1

公开(公告)日：2008-12-25

申请号：US11819042

申请日：2007-06-25

申请人： S. Brad Herner ,  Mark H. Clark ,  Tanmay Kumar

发明人： S. Brad Herner ,  Mark H. Clark ,  Tanmay Kumar

IPC分类号： G11C11/00

CPC分类号： G11C11/36

摘要： A nonvolatile memory device includes at least one nonvolatile memory cell which comprises a silicon, germanium or silicon-germanium diode which is doped with at least one of carbon or nitrogen in a concentration greater than an unavoidable impurity level concentration.

摘要翻译： 非易失性存储器件包括至少一个非易失性存储单元，其包括硅，锗或硅 - 锗二极管，其掺杂有浓度大于不可避免的杂质水平浓度的碳或氮中的至少一种。

公开(公告)号：US20080239787A1

公开(公告)日：2008-10-02

申请号：US11692153

申请日：2007-03-27

申请人： S. Brad Herner

发明人： S. Brad Herner

IPC分类号： G11C11/00 ,  H01L27/08

CPC分类号： H01L45/122 ,  B82Y10/00 ,  G11C13/0007 ,  G11C17/16 ,  G11C2213/16 ,  G11C2213/32 ,  G11C2213/71 ,  H01L27/1021 ,  H01L27/24 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/149 ,  H01L45/16 ,  Y10S977/742 ,  Y10S977/842

摘要： An upward-pointing p-i-n diode formed of deposited silicon, germanium, or silicon-germanium is disclosed. The diode has a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region. The top heavily doped p-type region is doped with arsenic, and the semiconductor material of the diode is crystallized in contact with an appropriate silicide, germanide, or silicide-germanide. A large array of such upward-pointing diodes can be formed with excellent uniformity of current across the array when a voltage above the turn-on voltage of the diodes is applied. This diode is advantageously used in a monolithic three dimensional memory array.

摘要翻译： 公开了由沉积的硅，锗或硅 - 锗形成的向上指向的p-i-n二极管。 二极管具有底部重掺杂p型区域，中间固有或轻掺杂区域和顶部重掺杂n型区域。 顶部重掺杂p型区掺杂砷，二极管的半导体材料与适当的硅化物，锗化物或硅化锗 - 锗化物接触结晶。 当施加高于二极管的导通电压的电压时，可以形成具有优异的跨阵列电流均匀性的这种向上指向二极管的大阵列。 该二极管有利地用于单片三维存储器阵列中。

公开(公告)号：US20080119007A1

公开(公告)日：2008-05-22

申请号：US11560792

申请日：2006-11-16

申请人： Usha Raghuram ,  S. Brad Herner

发明人： Usha Raghuram ,  S. Brad Herner

IPC分类号： H01L47/00

CPC分类号： H01L45/144 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1683 ,  H01L45/1691

摘要： A method is described to form a nonvolatile memory cell having a contact area between a phase-change material such as a chalcogenide and a heat source which is smaller than photolithographic limits. A conductive or semiconductor pillar is exposed at a dielectric surface and recessed by selective etch. A thin, conformal layer of a spacer material is deposited on the dielectric top surface, the pillar top surface, and the sidewalls of the recess, then removed from horizontal surfaces by anistropic etch, leaving a spacer on the sidewalls defining a reduced volume within the recess. The phase change material is deposited within the spacer, having a reduced contact area to the underlying conductive or semiconductor pillar.

摘要翻译： 描述了一种形成非易失性存储单元的方法，所述非易失性存储单元具有诸如硫族化物的相变材料与小于光刻极限的热源之间的接触面积。 导电或半导体柱在电介质表面露出并通过选择性蚀刻凹陷。 间隔材料的薄的共形层被沉积在电介质顶表面，柱顶表面和凹槽的侧壁上，然后通过无功蚀刻从水平表面去除，在侧壁上留下间隔，限定内部减小的体积 休息。 相变材料沉积在间隔物内，具有减小的与下面的导电或半导体柱的接触面积。

公开(公告)号：US07276403B2

公开(公告)日：2007-10-02

申请号：US11237162

申请日：2005-09-28

申请人： S. Brad Herner

发明人： S. Brad Herner

IPC分类号： H01L21/84

CPC分类号： H01L27/1021 ,  H01L21/84 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/12

摘要： The present invention relates to use of selective oxidation to oxidize silicon in the presence of tungsten and/or tungsten nitride in memory cells and memory arrays. This technique is especially useful in monolithic three dimensional memory arrays. In one aspect of the invention, the silicon of a diode-antifuse memory cell is selectively oxidized to repair etch damage and reduce leakage, while exposed tungsten of adjacent conductors and tungsten nitride of a barrier layer are not oxidized. In some embodiments, selective oxidation may be useful for gap fill. In another aspect of the invention, TFT arrays made up of charge storage memory cells comprising a polysilicon/tungsten nitride/tungsten gate can be subjected to selective oxidation to passivate the gate polysilicon and reduce leakage.

摘要翻译： 本发明涉及选择性氧化在存在于存储器单元和存储器阵列中的钨和/或氮化钨存在下氧化硅的用途。 这种技术在单片三维存储器阵列中特别有用。 在本发明的一个方面，二极管 - 反熔断存储器单元的硅被选择性地氧化以修复蚀刻损伤并减少泄漏，而相邻导体的暴露的钨和阻挡层的氮化钨不被氧化。 在一些实施方案中，选择性氧化可用于间隙填充。 在本发明的另一方面，可以对包括多晶硅/氮化钨/钨栅极的电荷存储单元组成的TFT阵列进行选择性氧化，以钝化栅多晶硅并减少泄漏。

公开(公告)号：US07238607B2

公开(公告)日：2007-07-03

申请号：US11237169

申请日：2005-09-28

申请人： Samuel V. Dunton ,  S. Brad Herner

发明人： Samuel V. Dunton ,  S. Brad Herner

IPC分类号： H01L21/4763

CPC分类号： G11C11/39 ,  G11C5/02 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/77

摘要： When chemical mechanical planarization (CMP) is used to planarize a surface coexposing patterned features and dielectric fill, where patterned features and the fill are formed of materials having very different CMP removal rates or characteristics, the planarized surface may have excessively rough, dishing or recessing may take place, or one or more or the materials may be damaged. In structures in which planarity is important, these problems can be prevented by forming a capping layer on the patterned features, wherein the CMP removal rate of the material forming the capping layer is similar to the CMP removal rate of the dielectric fill.

摘要翻译： 当化学机械平面化（CMP）用于平坦化表面共同图案化特征和电介质填充时，其中图案特征和填充物由具有非常不同的CMP去除速率或特性的材料形成，平坦化表面可能具有过度粗糙，凹陷或凹陷 可能发生，或者一个或多个，或者材料可能被损坏。 在平面度重要的结构中，通过在图案化特征上形成覆盖层可以防止这些问题，其中形成覆盖层的材料的CMP去除速率类似于介电填料的CMP去除速率。

公开(公告)号：US06956278B2

公开(公告)日：2005-10-18

申请号：US10611245

申请日：2003-06-30

申请人： S. Brad Herner

发明人： S. Brad Herner

IPC分类号： H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L23/525 ,  H01L29/49 ,  H01L29/78 ,  H01L29/00 ,  H01L29/04

CPC分类号： H01L23/5252 ,  H01L21/28088 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/2855 ,  H01L21/3205 ,  H01L28/60 ,  H01L29/4966 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A low-density, high-resistivity layer of a PVD sputter-deposited material, preferably titanium nitride, when coupled with a dielectric, makes a superior low-leakage insulating barrier for use in semiconductor devices. The material is created by sputtering methods that cause the ions to strike the deposition surface with reduced energy, for example in an ion metal plasma chamber with no self-bias accelerating ions normal to the deposition surface, or in a standard PVD chamber with pressure increased.

摘要翻译： 当与电介质耦合时，PVD溅射沉积材料（优选氮化钛）的低密度，高电阻率层产生用于半导体器件的优异的低漏电绝缘屏障。 该材料是通过溅射方法产生的，这些方法使离子以较低的能量冲击沉积表面，例如在离子金属等离子体室中，没有自偏压加速垂直于沉积表面的离子，或者在具有压力增加的标准PVD室中 。

公开(公告)号：US06815077B1

公开(公告)日：2004-11-09

申请号：US10441601

申请日：2003-05-20

申请人： S. Brad Herner ,  Mark H. Clark

发明人： S. Brad Herner ,  Mark H. Clark

IPC分类号： B32B1504

CPC分类号： H01L21/8221 ,  C23C16/045 ,  C23C16/24 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/28525 ,  H01L27/1052

摘要： A method to create a low resistivity P+ in-situ doped polysilicon film at low temperature from SiH4 and BCl3 with no anneal required. At conventional dopant concentrations using these source gases, as deposition temperature decreases below about 550 degrees C., deposition rate decreases and sheet resistance increases, making production of a high-quality film impossible. By flowing very high amounts of BCl3, however, such that the concentration of boron atoms in the resultant film is about 7×1020 or higher, the deposition rate and sheet resistance are improved, and a high-quality film is produced.

摘要翻译： 在低温下从SiH4和BCl3生成低电阻P +原位掺杂多晶硅膜的方法，无需退火。 在使用这些源气体的常规掺杂剂浓度下，随着沉积温度降低到约550℃以下，沉积速率降低并且薄层电阻增加，使得生产高质量膜不可能。 然而，通过流动非常大量的BCl 3，使得所得膜中硼原子的浓度为约7×10 20或更高，沉积速率和薄层电阻提高，并且产生高质量的膜。

公开(公告)号：US09070801B2

公开(公告)日：2015-06-30

申请号：US13446051

申请日：2012-04-13

申请人： S. Brad Herner

发明人： S. Brad Herner

IPC分类号： H01L21/00 ,  H01L31/0236 ,  H01L31/028 ,  H01L31/0392 ,  H01L31/18

CPC分类号： H01L31/0236 ,  H01L31/02363 ,  H01L31/028 ,  H01L31/03921 ,  H01L31/1804 ,  H01L31/1892 ,  Y02E10/547 ,  Y02E10/548 ,  Y02P70/521

摘要： It is advantageous to create texture at the surface of a photovoltaic cell to reduce reflection and increase travel length of light within the cell. A method is disclosed to create texture at the surface of a silicon body by reacting a silicide-forming metal at the surface, where the silicide-silicon interface is non-planar, then stripping the silicide, leaving behind a textured surface. Depending on the metal and the conditions of silicide formation, the resulting surface may be faceted. The peak-to-valley height of this texturing will generally be between about 300 and about 5000 angstroms, which is well-suited for use in photovoltaic cells comprising a thin silicon lamina.

摘要翻译： 有利的是在光伏电池的表面处产生纹理以减少反射并增加电池内的光的行进长度。 公开了一种通过使表面处的硅化物形成金属（其中硅化物 - 硅界面是非平面的）反应然后剥离硅化物，留下纹理表面来在硅体的表面上产生纹理的方法。 取决于金属和硅化物形成的条件，所得到的表面可以是刻面的。 该纹理的峰谷高度通常在约300至约5000埃之间，这非常适用于包含薄硅层的光伏电池。

公开(公告)号：US08987119B2

公开(公告)日：2015-03-24

申请号：US13026381

申请日：2011-02-14

申请人： Vance Dunton ,  S. Brad Herner ,  Paul Wai Kie Poon ,  Chuanbin Pan ,  Michael Chan ,  Michael Konevecki ,  Usha Raghuram

发明人： Vance Dunton ,  S. Brad Herner ,  Paul Wai Kie Poon ,  Chuanbin Pan ,  Michael Chan ,  Michael Konevecki ,  Usha Raghuram

IPC分类号： H01L21/36 ,  H01L27/102 ,  H01L29/861 ,  H01L29/868

CPC分类号： H01L27/1021 ,  H01L29/8613 ,  H01L29/8615 ,  H01L29/868

摘要： A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer. The second conductivity type second portions of the second semiconductor layer remain in upper portions of the plurality of openings in the insulating layer to form a plurality of pillar shaped diodes in the plurality of openings.