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    RESISTANCE TYPE MEMORY DEVICE
    53.
    发明申请
    RESISTANCE TYPE MEMORY DEVICE 有权
    电阻型存储器件

    公开(公告)号：US20090166604A1

    公开(公告)日：2009-07-02

    申请号：US12403186

    申请日：2009-03-12

    申请人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

    发明人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

    IPC分类号： H01L27/24

    CPC分类号： G11C11/54 ,  G11C11/14 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  Y10S438/972

    摘要： A resistance type memory device is provided. The resistance type memory device includes a first and a second conductors and a metal oxide layer. The metal oxide layer is disposed between the first and the second conductors, and the resistance type memory device is defined in a first resistivity. The resistance type memory device is defined in a second resistivity after a first pulse voltage is applied to the metal oxide layer. The resistance type memory device is defined in a third resistivity after a second pulse voltage is applied to the metal oxide layer. The second resistivity is greater than the first resistivity, and the first resistivity is greater than the third resistivity.

    摘要翻译： 提供电阻型存储器件。 电阻型存储器件包括第一和第二导体和金属氧化物层。 金属氧化物层设置在第一和第二导体之间，电阻型存储装置被定义为第一电阻率。 在向金属氧化物层施加第一脉冲电压之后，将电阻型存储器件定义为第二电阻率。 在向金属氧化物层施加第二脉冲电压之后，将电阻型存储器件定义为第三电阻率。 第二电阻率大于第一电阻率，第一电阻率大于第三电阻率。

    METHOD FOR FORMING SELF-ALIGNED THERMAL ISOLATION CELL FOR A VARIABLE RESISTANCE MEMORY ARRAY
    54.
    发明申请
    METHOD FOR FORMING SELF-ALIGNED THERMAL ISOLATION CELL FOR A VARIABLE RESISTANCE MEMORY ARRAY 有权
    形成可变电阻记忆阵列的自对准热隔离单元的方法

    公开(公告)号：US20090148981A1

    公开(公告)日：2009-06-11

    申请号：US12351692

    申请日：2009-01-09

    申请人： Erh-Kun Lai ,  Chiahua Ho ,  Kuang Yeu Hsieh

    发明人： Erh-Kun Lai ,  Chiahua Ho ,  Kuang Yeu Hsieh

    IPC分类号： H01L21/00

    CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1683

    摘要： A non-volatile memory with a self-aligned RRAM element includes a lower electrode element, generally planar in form, having an inner contact surface; an upper electrode element, spaced from the lower electrode element; a containment structure extends between the upper electrode element and the lower electrode element, with a sidewall spacer element having a generally funnel-shaped central cavity with a central aperture; and a spandrel element positioned between the sidewall spacer element and the lower electrode. A RRAM element extends between the lower electrode element and the upper electrode, occupying at least a portion of the sidewall spacer element central cavity and projecting from the sidewall spacer terminal edge toward and making contact with the lower electrode. In this manner, the spandrel element inner surface is spaced from the RRAM element to define a thermal isolation cell adjacent the RRAM element.

    摘要翻译： 具有自对准RRAM元件的非易失性存储器包括具有内接触表面的大体平面形状的下电极元件; 与所述下电极元件间隔开的上电极元件; 容纳结构在上电极元件和下电极元件之间延伸，侧壁间隔元件具有大致漏斗形的具有中心孔的中心腔; 以及位于侧壁间隔元件和下电极之间的突出元件。 RRAM元件在下电极元件和上电极之间延伸，占据侧壁间隔件元件中心腔的至少一部分并且从侧壁间隔件端子边缘朝向和与下电极接触。 以这种方式，伞形元件内表面与RRAM元件间隔开以限定与RRAM元件相邻的热隔离单元。

    MEMORY CELL AND PROCESS FOR MANUFACTURING THE SAME
    55.
    发明申请
    MEMORY CELL AND PROCESS FOR MANUFACTURING THE SAME 有权
    存储单元及其制造方法

    公开(公告)号：US20080237798A1

    公开(公告)日：2008-10-02

    申请号：US11867000

    申请日：2007-10-04

    申请人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

    发明人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

    IPC分类号： H01L27/06 ,  H01L21/02

    CPC分类号： H01L27/101 ,  H01L28/20 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1675

    摘要： A memory cell and a process for manufacturing the same are provided. In the process, a first electrode layer is formed on a conductive layer over a substrate, and then a transition metal layer is formed on the first electrode layer. After that, the transition metal layer is subjected to a plasma oxidation step to form a transition metal oxide layer as a precursor of a data storage layer, and a second electrode layer is formed on the transition metal oxide layer. A memory cell is formed after the second electrode layer, the transition metal oxide layer and the first electrode layer are patterned into a second electrode, a data storage layer and a first electrode, respectively.

    摘要翻译： 提供了一种存储单元及其制造方法。 在该工艺中，在衬底上的导电层上形成第一电极层，然后在第一电极层上形成过渡金属层。 之后，对过渡金属层进行等离子体氧化工序，形成作为数据存储层的前体的过渡金属氧化物层，在过渡金属氧化物层上形成第二电极层。 在第二电极层，过渡金属氧化物层和第一电极层分别形成第二电极，数据存储层和第一电极之后形成存储单元。

    Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states
    56.
    发明授权
    Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states 有权
    操作具有多个存储器层和多级存储器状态的双稳态电阻随机存取存储器的方法

    公开(公告)号：US07388771B2

    公开(公告)日：2008-06-17

    申请号：US11552464

    申请日：2006-10-24

    申请人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    发明人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    IPC分类号： G11C11/00

    CPC分类号： G11C17/165 ,  B82Y10/00 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/0069 ,  G11C17/16 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/77

    摘要： A method is described for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is disclosed. The bistable resistance random access memory comprises two memory layer stacks per memory cell, the bistable resistance random access memory operates in four logic states, a logic “00” state, a logic “01” state, a logic “10” state and a logic “11” state. The relationship between the four different logic states can be represented mathematically by the two variables n and f and a resistance R. The logic “0” state is represented by a mathematical expression (1+f)R. The logic “1” state is represented by a mathematical expression (n+f)R. The logic “2” state is represented by a mathematical expression (1+nf)R. The logic “3” state is represented by a mathematical expression n(1+f)R.

    摘要翻译： 描述了一种用于操作具有串联排列的两个存储层堆叠的双稳态电阻随机存取存储器的方法。 双稳态电阻随机存取存储器包括每个存储单元的两个存储层堆栈，双稳态电阻随机存取存储器以四个逻辑状态，逻辑“00”状态，逻辑“01”状态，逻辑“10”状态和逻辑 “11”状态。 四个不同逻辑状态之间的关系可以由两个变量n和f以及电阻R在数学上表示。逻辑“0”状态由数学表达式（1 + f）R表示。 逻辑“1”状态由数学表达式（n + f）R表示。 逻辑“2”状态由数学表达式（1 + nf）R表示。 逻辑“3”状态由数学表达式n（1 + f）R表示。

    Resistance Random Access Memory Structure for Enhanced Retention
    57.
    发明申请
    Resistance Random Access Memory Structure for Enhanced Retention 有权
    电阻随机存取存储结构，用于增强保留

    公开(公告)号：US20080116440A1

    公开(公告)日：2008-05-22

    申请号：US11560723

    申请日：2006-11-16

    申请人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    发明人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    IPC分类号： H01L47/00

    CPC分类号： H01L45/1608 ,  H01L45/04 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1625

    摘要： A bistable resistance random access memory is described for enhancing the data retention in a resistance random access memory member. A dielectric member, e.g. the bottom dielectric member, underlies the resistance random access memory member which improves the SET/RESET window in the retention of information. The deposition of the bottom dielectric member is carried out by a plasma-enhanced chemical vapor deposition or by high-density-plasma chemical vapor deposition. One suitable material for constructing the bottom dielectric member is a silicon oxide. The bistable resistance random access memory includes a bottom dielectric member disposed between a resistance random access member and a bottom electrode or bottom contact plug. Additional layers including a bit line, a top contact plug, and a top electrode disposed over the top surface of the resistance random access memory member. Sides of the top electrode and the resistance random access memory member are substantially aligned with each other.

    摘要翻译： 描述了双稳态电阻随机存取存储器，用于增强电阻随机存取存储器件中的数据保持。 电介质构件，例如 底部电介质构件位于电阻随机存取存储器构件的下方，其改善了保留信息中的SET / RESET窗口。 底部电介质构件的沉积通过等离子体增强化学气相沉积或通过高密度 - 等离子体化学气相沉积来进行。 用于构造底部电介质构件的一种合适的材料是氧化硅。 双稳态随机存取存储器包括设置在电阻随机存取构件和底部电极或底部接触插塞之间的底部电介质构件。 附加层包括位线，顶部接触插塞和设置在电阻随机存取存储器构件顶表面上的顶部电极。 顶部电极和电阻随机存取存储器构件的侧面基本上彼此对准。

    RESISTOR RANDOM ACCESS MEMORY CELL WITH REDUCED ACTIVE AREA AND REDUCED CONTACT AREAS
    59.
    发明申请
    RESISTOR RANDOM ACCESS MEMORY CELL WITH REDUCED ACTIVE AREA AND REDUCED CONTACT AREAS 有权
    电阻随机访问存储单元，具有减少的活动区域和减少的接触区域

    公开(公告)号：US20070281420A1

    公开(公告)日：2007-12-06

    申请号：US11421042

    申请日：2006-05-30

    申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

    发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

    IPC分类号： H01L21/8242

    CPC分类号： H01L45/04 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/14 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1675 ,  Y10S438/90

    摘要： A memory device has a sidewall insulating member with a sidewall insulating member length according to a first spacer layer thickness. A first electrode formed from a second spacer layer having a first electrode length according to a thickness of a second spacer layer and a second electrode formed from the second spacer layer having a second electrode length according to the thickness of the second spacer layer are formed on sidewalls of the sidewall insulating member. A bridge of memory material having a bridge width extends from a top surface of the first electrode to a top surface of the second electrode across a top surface of the sidewall insulating member, wherein the bridge comprises memory material.

    摘要翻译： 存储器件具有侧壁绝缘构件，其具有根据第一间隔层厚度的侧壁绝缘构件长度。 由具有根据第二间隔层的厚度的第一电极长度和根据第二间隔层的厚度具有第二电极长度的由第二间隔层形成的第二电极的第二间隔层形成的第一电极形成在 侧壁绝缘部件的侧壁。 具有桥接宽度的记忆材料桥由第一电极的顶表面延伸穿过侧壁绝缘构件的顶表面延伸到第二电极的顶表面，其中桥包括记忆材料。

    Resistance type memory device
    60.
    发明授权
    Resistance type memory device 有权
    电阻型记忆装置

    公开(公告)号：US08927956B2

    公开(公告)日：2015-01-06

    申请号：US12403186

    申请日：2009-03-12

    申请人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

    发明人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

    IPC分类号： H01L45/00 ,  G11C11/00 ,  G11C13/00 ,  G11C11/54 ,  G11C11/14 ,  G11C11/56

    CPC分类号： G11C11/54 ,  G11C11/14 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  Y10S438/972

    摘要： A resistance type memory device is provided. The resistance type memory device includes a first and a second conductors and a metal oxide layer. The metal oxide layer is disposed between the first and the second conductors, and the resistance type memory device is defined in a first resistivity. The resistance type memory device is defined in a second resistivity after a first pulse voltage is applied to the metal oxide layer. The resistance type memory device is defined in a third resistivity after a second pulse voltage is applied to the metal oxide layer. The second resistivity is greater than the first resistivity, and the first resistivity is greater than the third resistivity.

    摘要翻译： 提供电阻型存储器件。 电阻型存储器件包括第一和第二导体和金属氧化物层。 金属氧化物层设置在第一和第二导体之间，电阻型存储装置被定义为第一电阻率。 在向金属氧化物层施加第一脉冲电压之后，将电阻型存储器件定义为第二电阻率。 在向金属氧化物层施加第二脉冲电压之后，将电阻型存储器件定义为第三电阻率。 第二电阻率大于第一电阻率，第一电阻率大于第三电阻率。