公开(公告)号：US20140353842A1

公开(公告)日：2014-12-04

申请号：US13908096

申请日：2013-06-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Juhan Kim ,  Jongwook Kye ,  Mahbub Rashed

IPC: G06F17/50 ,  H01L23/522

CPC classification number: G06F17/5077 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size.

Abstract translation: 本文描述的实施例提供了使用宽边缘引脚改进电路布线的方法。 具体地，提供了一种集成电路（IC）装置，其包括具有在通孔处连接到第二金属层（M2）线的第一金属层（M1）引脚的标准单元。 M1引脚的宽度大于通孔的宽度，足以满足通孔的外壳规则，而M1引脚垂直延伸超过基本上等于或大于零的距离。 该布局增加了标准单元内可用引脚接入点的数量，从而提高了布线效率和芯片尺寸。

公开(公告)号：US20140339610A1

公开(公告)日：2014-11-20

申请号：US13893684

申请日：2013-05-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mahbub Rashed ,  Juhan Kim ,  Yunfei Deng ,  Jongwook Kye ,  Suresh Venkatesan

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/6681

Abstract: Embodiments of the present invention provide a novel method and structure for forming finFET structures that comprise standard cells. An H-shaped cut mask is used to reduce the number of fins that need to be removed, hence increasing the fin efficiency.

Abstract translation: 本发明的实施例提供了用于形成包含标准单元的finFET结构的新颖方法和结构。 使用H形切割掩模来减少需要去除的翅片的数量，从而提高翅片效率。

公开(公告)号：US20140208285A1

公开(公告)日：2014-07-24

申请号：US13746508

申请日：2013-01-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jongwook Kye ,  Harry J. Levinson ,  Jason E. Stephens ,  Lei Yuan

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/70 ,  G06F17/5068

Abstract: A design methodology for determining a via enclosure rule for use with a self-aligned double pattern (SADP) technique is disclosed. The shape of the block mask serves as a criterion for choosing a via enclosure rule. Different block mask shapes within an integrated circuit design may utilize different rules and provide different margins for via enclosure. A tight via enclosure design rule reduces the margin of a line beyond the via where possible, while a loose via enclosure design rule increases the margin of a line beyond the via where it is beneficial to do so.

Abstract translation: 公开了一种用于确定与自对准双重图案（SADP）技术一起使用的通孔外壳规则的设计方法。 块掩模的形状作为选择通孔封套规则的标准。 集成电路设计中不同的块掩模形状可以利用不同的规则，并为通孔外壳提供不同的边缘。 紧密的通孔外壳设计规则可能会减少超出通孔的线的余量，而松动的通孔外壳设计规则可增加超出通孔的线的裕度，从而有利于此。

公开(公告)号：US08789000B1

公开(公告)日：2014-07-22

申请号：US13863591

申请日：2013-04-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mahbub Rashed ,  Lei Yuan ,  Jongwook Kye ,  Suresh Venkatesan

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A system and design methodology for performing routing in an integrated circuit design is disclosed. An integrated circuit design is first created using standard cells having metal level 2 (M2) power rails. Routing is performed and power rail current density for the integrated circuit is computed. Standard cells that have power rail current density below a predetermined threshold are replaced with a functionally equivalent standard cell that does not have M2 power rails, and the routing operation is performed again, until the design converges.

Abstract translation: 公开了一种用于在集成电路设计中执行路由的系统和设计方法。 首先使用具有金属级2（M2）电源轨的标准单元创建集成电路设计。 执行路由，并计算集成电路的电源轨电流密度。 具有低于预定阈值的电力轨电流密度的标准电池被替换为不具有M2电力轨的功能等效的标准单元，并且直到设计收敛为止，再次执行路由操作。

公开(公告)号：US20180033701A1

公开(公告)日：2018-02-01

申请号：US15728445

申请日：2017-10-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Andy Chi-Hung Wei ,  Jia Zeng ,  Jongwook Kye ,  Jason Eugene Stephens ,  Irene Yuh-Ling Lin ,  Sudharshanan Raghunathan ,  Lei Yuan

IPC: H01L21/8238 ,  H01L23/535 ,  H01L21/027 ,  G06F17/50 ,  H01L21/768 ,  H01L21/285 ,  H01L27/092 ,  H01L21/8234

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

公开(公告)号：US09818651B2

公开(公告)日：2017-11-14

申请号：US15067953

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Andy Chi-Hung Wei ,  Jia Zeng ,  Jongwook Kye ,  Jason Eugene Stephens ,  Irene Yuh-Ling Lin ,  Sudharshanan Raghunathan ,  Lei Yuan

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/285 ,  H01L21/027 ,  H01L27/092 ,  H01L23/535 ,  G06F17/50

CPC classification number: H01L21/823871 ,  G06F17/5072 ,  H01L21/027 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

公开(公告)号：US09798852B2

公开(公告)日：2017-10-24

申请号：US15040235

申请日：2016-02-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jongwook Kye ,  Harry J. Levinson

IPC: G06F17/50 ,  H01L21/027

CPC classification number: G06F17/5081 ,  G06F2217/12 ,  H01L21/027

Abstract: Methods for performing design rule checking of a circuit design are provided. The methods include, for instance: providing a circuit design for an integrated circuit layer, in which the circuit design includes a plurality of design lines oriented in a particular direction; and automatically performing a design rule check of the circuit design, which may include forming a verification pattern for the circuit design, the verification pattern comprising a plurality of verification lines and a plurality of verification regions, wherein one or more verification regions are associated with and connected to one verification line of the plurality of verification lines, and checking the verification pattern for any verification line overlapping a verification region. The circuit design may be considered to fail the design rule check if an end of one verification line overlaps any verification region associated with another verification line of the verification pattern.

公开(公告)号：US20170221886A1

公开(公告)日：2017-08-03

申请号：US15490702

申请日：2017-04-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Mark A. Zaleski ,  Tuhin Guha Neogi ,  Jason E. Stephens ,  Jongwook Kye ,  Jia Zeng

IPC: H01L27/088 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28568 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/5329 ,  H01L27/092 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/66462 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.

公开(公告)号：US09536035B2

公开(公告)日：2017-01-03

申请号：US14809698

申请日：2015-07-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Juhan Kim ,  Jongwook Kye ,  Mahbub Rashed

IPC: H01L23/52 ,  G06F17/50 ,  H01L23/522 ,  H01L27/02 ,  H01L27/118

CPC classification number: G06F17/5077 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size.

Abstract translation: 本文描述的实施例提供了使用宽边缘引脚改进电路布线的方法。 具体地，提供了一种集成电路（IC）装置，其包括具有在通孔处耦合到第二金属层（M2）线的第一金属层（M1）引脚的标准单元。 M1引脚的宽度大于通孔的宽度，足以满足通孔的外壳规则，而M1引脚垂直延伸超过基本上等于或大于零的距离。 该布局增加了标准单元内可用引脚接入点的数量，从而提高了布线效率和芯片尺寸。

公开(公告)号：US09472464B1

公开(公告)日：2016-10-18

申请号：US15060691

申请日：2016-03-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jia Zeng ,  Lei Yuan ,  Youngtag Woo ,  Yan Wang ,  Jongwook Kye

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/308

CPC classification number: H01L21/823821 ,  H01L21/3086 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/785

Abstract: Methods for processes to form and use merged spacers in fin generation and the resulting devices are disclosed. Embodiments include providing first and second mandrels separated from each other across adjacent cells on a Si layer; forming first and second dummy-spacers and third and fourth dummy-spacers on opposite sides of the first and second mandrels, respectively; removing, through a block-mask, the first and fourth dummy spacers and a portion of the second and third dummy-spacers; forming first spacers on each exposed side of the mandrels and in between the second and third dummy-spacers, forming a merged spacer; removing the mandrels; removing a section of the merged-spacer; forming second spacers on all exposed sides of the first spacers and the merged-spacer; removing the merged-spacer and the first spacers; removing exposed sections of the Si layer through the second spacers; and removing the second spacers to reveal Si fins.

Abstract translation: 公开了在翅片生成中形成和使用合并间隔物的方法以及所得装置。 实施例包括提供在Si层上相邻的单元彼此分开的第一和第二心轴; 在第一和第二心轴的相对侧分别形成第一和第二虚拟间隔物和第三和第四虚拟间隔物; 通过块掩模去除第一和第四虚拟间隔物和第二和第三虚拟间隔物的一部分; 在心轴的每个暴露侧上并在第二和第三虚拟间隔件之间形成第一间隔件，形成合并间隔件; 去除心轴; 去除合并间隔物的一部分; 在第一间隔件和合并间隔件的所有暴露侧上形成第二间隔件; 去除合并间隔物和第一间隔物; 通过所述第二间隔物去除所述Si层的暴露部分; 并且移除第二间隔件以露出Si散热片。