公开(公告)号：US10818763B1

公开(公告)日：2020-10-27

申请号：US16405368

申请日：2019-05-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  Michel J. Abou-Khalil ,  Siva P. Adusumilli

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/45 ,  H01L27/088

Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A first gate electrode has a first plurality of segments arranged in series to define a first non-rectilinear chain. A second gate electrode is arranged adjacent to the first gate electrode. The second gate electrode includes a second plurality of segments arranged in series to define a second non-rectilinear chain. A source/drain region is laterally arranged between the first gate electrode and the second gate electrode.

公开(公告)号：US10795083B1

公开(公告)日：2020-10-06

申请号：US16426551

申请日：2019-05-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob ,  Steven M. Shank

IPC: G02B6/125 ,  G02B6/122 ,  G02B6/13 ,  G02B6/12

Abstract: Structures for a directional coupler and methods of fabricating a structure for a directional coupler. A first section of a first waveguide core is laterally spaced from a second section of a second waveguide core. A coupling element is arranged either over or under the first section of the first waveguide core and the second section of the second waveguide core. The first and second waveguide cores are comprised of a material having a first refractive index, and the first coupling element is comprised of a material having a second refractive index that is different from the first refractive index. The first coupling element is surrounded by a side surface that overlaps with the first section of the first waveguide core and the second section of the second waveguide core.

公开(公告)号：US10446435B2

公开(公告)日：2019-10-15

申请号：US15951557

申请日：2018-04-12

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Steven M. Shank ,  Michel Abou-Khalil

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84

Abstract: A trap-rich polysilicon layer is interposed between the active (SOI) layer and the underlying handle portion of a semiconductor substrate to prevent or minimize parasitic surface conduction effects within the active layer and promote device linearity. In various embodiments, the trap-rich layer extends vertically through a portion of an isolation layer and laterally therefrom between the isolation layer and the handle portion of the substrate to underlie a portion of the device active area.

公开(公告)号：US10393960B1

公开(公告)日：2019-08-27

申请号：US15905165

申请日：2018-02-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Siva P. Adusumilli

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/136 ,  G02B6/132 ,  G02B6/13

Abstract: Waveguide structures and methods of fabricating waveguide structures. A first airgap is formed in a bulk semiconductor substrate, and a semiconductor layer is epitaxially grown over the bulk semiconductor substrate and the first airgap. First and second trench isolation regions extend through the semiconductor layer and into the bulk semiconductor substrate, and are spaced to define a waveguide core region including a section of the bulk semiconductor substrate and a section of the semiconductor layer that are arranged between the first and second trench isolation regions. A dielectric layer is formed over the waveguide core region, and a second airgap is formed in the dielectric layer. The first airgap is arranged in the bulk semiconductor substrate between the first trench isolation region and the second trench isolation region and under the waveguide core region. The second airgap in the dielectric layer is arranged over the waveguide core region.

公开(公告)号：US10243047B2

公开(公告)日：2019-03-26

申请号：US15372929

申请日：2016-12-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  John J. Ellis-Monaghan

IPC: H01L29/10 ,  H01L29/06 ,  H01L23/66 ,  H01L21/762 ,  H01L29/78 ,  H01L25/18 ,  H01L21/764 ,  H01L21/8234

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to active and passive radio frequency (RF) components with deep trench isolation structures and methods of manufacture. The structure includes a bulk high resistivity wafer with a deep trench isolation structure having a depth deeper than a maximum depletion depth at worst case voltage bias difference between devices which are formed on the bulk high resistivity wafer.

公开(公告)号：US10156676B1

公开(公告)日：2018-12-18

申请号：US15905134

申请日：2018-02-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Siva P. Adusumilli

IPC: G02B6/122 ,  G02B6/13 ,  G02B6/136 ,  G02B6/12 ,  H01L31/0232 ,  H01L31/113

Abstract: Waveguide structures and methods of fabricating waveguide structures. The waveguide structures are formed using a semiconductor substrate that includes a device layer, a handle wafer, a buried oxide layer between the handle wafer and the device layer, and an epitaxial semiconductor layer over the device layer. First and second trench isolation regions extend through the device layer and the epitaxial semiconductor layer. The first and second trench isolation regions are spaced to define a waveguide core region comprising a section of the device layer and a section of the epitaxial semiconductor layer that are arranged between the first and second trench isolation regions. A first airgap and a second airgap are respectively located in the device layer and the buried oxide layer. The first and second airgaps are arranged beneath the waveguide core region, and the first airgap may be arranged between the second airgap and the waveguide core region.

公开(公告)号：US09991155B2

公开(公告)日：2018-06-05

申请号：US15281418

申请日：2016-09-30

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Steven M. Shank ,  Michel Abou-Khalil

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/76286 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

Abstract: A trap-rich polysilicon layer is interposed between the active (SOI) layer and the underlying handle portion of a semiconductor substrate to prevent or minimize parasitic surface conduction effects within the active layer and promote device linearity. In various embodiments, the trap-rich layer extends vertically through a portion of an isolation layer and laterally therefrom between the isolation layer and the handle portion of the substrate to underlie a portion of the device active area.

公开(公告)号：US09806221B2

公开(公告)日：2017-10-31

申请号：US15441345

申请日：2017-02-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven M. Shank ,  John J. Ellis-Monaghan ,  Marwan H. Khater ,  Jason S. Orcutt

IPC: H01L31/105 ,  H01L31/0232 ,  H01L31/18 ,  H01L31/0392 ,  H01L31/0312 ,  H01L31/0352 ,  H01L31/103

CPC classification number: H01L31/1812 ,  H01L31/022408 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/035272 ,  H01L31/03529 ,  H01L31/03921 ,  H01L31/1037 ,  H01L31/109 ,  H01L31/1864 ,  H01L31/1872 ,  Y02E10/50

Abstract: Various particular embodiments include a method for forming a photodetector, including: forming a structure including a barrier layer disposed between a layer of doped silicon (Si) and a layer of germanium (Ge), the barrier layer including a crystallization window; and annealing the structure to convert, via the crystallization window, the Ge to a first composition of silicon germanium (SiGe) and the doped Si to a second composition of SiGe.

公开(公告)号：US09799693B2

公开(公告)日：2017-10-24

申请号：US15215674

申请日：2016-07-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  Qizhi Liu ,  Steven M. Shank

IPC: H01L27/146 ,  H01L21/762 ,  H01L31/0232

CPC classification number: H01L27/14632 ,  G02B6/4202 ,  H01L21/76224 ,  H01L21/76283 ,  H01L27/1462 ,  H01L27/1463 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/0232 ,  H01L31/02327 ,  H01L31/101

Abstract: Disclosed are structures and methods of forming the structures so as to have a photodetector isolated from a substrate by stacked trench isolation regions. In one structure, a first trench isolation region is in and at the top surface of a substrate and a second trench isolation region is in the substrate below the first. A photodetector is on the substrate aligned above the first and second trench isolation regions. In another structure, a semiconductor layer is on an insulator layer and laterally surrounded by a first trench isolation region. A second trench isolation region is in and at the top surface of a substrate below the insulator layer and first trench isolation region. A photodetector is on the semiconductor layer and extends laterally onto the first trench isolation region. The stacked trench isolation regions provide sufficient isolation below the photodetector to allow for direct coupling with an off-chip optical fiber.

公开(公告)号：US09703036B2

公开(公告)日：2017-07-11

申请号：US15041103

申请日：2016-02-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhong-Xiang He ,  Qizhi Liu ,  Ronald G. Meunier ,  Steven M. Shank

IPC: G02B6/12 ,  G02B6/42 ,  G02B6/122 ,  G02B6/136 ,  G02B6/132

CPC classification number: G02B6/12002 ,  G02B6/122 ,  G02B6/132 ,  G02B6/136 ,  G02B6/42 ,  G02B2006/121 ,  G02B2006/12119

Abstract: Disclosed are structures with an optical waveguide having a first segment at a first level and a second segment extending between the first level and a higher second level and further extending along the second level. Specifically, the waveguide comprises a first segment between first and second dielectric layers. The second dielectric layer has a trench, which extends through to the first dielectric layer and which has one side positioned laterally adjacent to an end of the first segment. The waveguide also comprises a second segment extending from the bottom of the trench on the side adjacent to the first segment up to and along the top surface of the second dielectric layer on the opposite side of the trench. A third dielectric layer covers the second segment in the trench and on the top surface of the second dielectric layer. Also disclosed are methods of forming such optoelectronic structures.