公开(公告)号：US20200173959A1

公开(公告)日：2020-06-04

申请号：US16203769

申请日：2018-11-29

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Eng Huat Toh ,  Bin Liu ,  Shyue Seng Tan ,  Kiok Boone Elgin Quek

IPC: G01N27/414 ,  H01L27/12

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a detection layer, a substrate, and a transistor having a transistor gate electrode, a transistor source, and a transistor drain. A capacitor gate electrode overlies the substrate, where the capacitor gate electrode and the transistor gate electrode are electrically connected with each other and with the detection layer. A capacitor well is defined within the substrate, and a gate insulator is positioned between the capacitor well and the capacitor gate electrode. A capacitor includes the capacitor gate electrode, the gate insulator, and the capacitor well.

公开(公告)号：US10608108B2

公开(公告)日：2020-03-31

申请号：US16013336

申请日：2018-06-20

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Chia Ching Yeo ,  Khee Yong Lim ,  Kiok Boone Elgin Quek ,  Donald R. Disney

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/12 ,  H01L29/08

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to extended drain MOSFET structures with a dual oxide thickness and methods of manufacture. The structure includes an extended drain metal oxide semiconductor transistor (EDMOS) comprising a gate structure with a dual oxide scheme.

公开(公告)号：US20190252514A1

公开(公告)日：2019-08-15

申请号：US16393028

申请日：2019-04-24

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Shyue Seng Tan ,  Kiok Boone Elgin Quek ,  Eng Huat Toh

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L23/535 ,  H01L29/51 ,  H01L23/522

Abstract: A semiconductor device with reduce capacitance coupling effect which can reduce the overall parasitic capacitances is disclosed. The semiconductor device includes a gate sidewall spacer with a negative capacitance dielectric layer with and without a dielectric layer. The semiconductor device may also include a plurality of interlevel dielectric (ILD) with a layer of negative capacitance dielectric layer followed by a dielectric layer disposed in-between metal lines in any ILD and combinations. The negative capacitance dielectric layer includes a ferroelectric material which has calculated and selected thicknesses with desired negative capacitance to provide optimal total overlap capacitance in the circuit component which aims to reduce the overall capacitance coupling effect.

公开(公告)号：US10103156B2

公开(公告)日：2018-10-16

申请号：US15434072

申请日：2017-02-16

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Xinshu Cai ,  Khee Yong Lim ,  Kiok Boone Elgin Quek

IPC: H01L27/115 ,  H01L21/82 ,  G11C16/04 ,  H01L27/11 ,  H01L27/11521 ,  H01L21/8234 ,  H01L27/11519 ,  H01L27/11507 ,  H01L27/11568 ,  H01L27/11504 ,  H01L27/1156 ,  H01L27/11563

Abstract: A device and methods for forming the device are disclosed. The method includes providing a substrate prepared with a memory cell region and forming memory cell pairs in the cell region. The memory cell pair comprises of first and second split gate memory cells. Each memory cell includes a first gate serving as an access gate, a second gate adjacent to the first gate, the second gate serving as a storage gate, a first source/drain (S/D) region adjacent to the first gate and a second S/D region adjacent to the second gate. The method also includes forming silicide contacts on the substrate on the gate conductors and first S/D regions and exposed buried common source lines (SLs) in pick-up regions, such that increasing the displacement distance in the wordline and source line (WLSL) region to an extended displacement distance DE avoids shorting between the first offset access gate conductors and adjacent access gate conductors of the rows of memory cell pairs.

公开(公告)号：US10096602B1

公开(公告)日：2018-10-09

申请号：US15459190

申请日：2017-03-15

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Shyue Seng Jason Tan ,  Kiok Boone Elgin Quek

IPC: H01L27/06 ,  H01L27/105 ,  H01L29/423 ,  H01L29/788 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/84

Abstract: Embodiments of a multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes an ultra-thin silicon-on-insulator (SOI) substrate. A transistor having a floating gate is disposed on the SOI substrate. The transistor comprises first and second source/drain (S/D) regions disposed adjacent to sides of the floating gate. A control capacitor having a control gate is disposed on the SOI substrate. The control gate is directly coupled to the floating gate. A device well is disposed in the base substrate and underlaps the floating gate and the control gate. A capacitor back-gate is embedded within the base substrate and in electrical communication with the control gate. A contact region is disposed within the device well.

公开(公告)号：US09978883B2

公开(公告)日：2018-05-22

申请号：US15472625

申请日：2017-03-29

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Yuan Sun ,  Shyue Seng Tan ,  Kiok Boone Elgin Quek

IPC: H01L21/00 ,  H01L29/94 ,  H01L27/12 ,  H01L29/06 ,  H01L27/08 ,  H01L29/66 ,  H01L21/84

CPC classification number: H01L29/94 ,  H01L21/823475 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0811 ,  H01L27/1203 ,  H01L28/40 ,  H01L29/0688 ,  H01L29/66189

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate with an active layer overlying a buried insulator layer that in turn overlies a handle layer, where the active layer includes a first active well. A first source, a first drain, and a first channel are defined within the first active well, where the first channel is between the first source and the first drain. A first gate dielectric directly overlies the first channel, and a first gate directly overlies the first gate dielectric, where a first capacitor includes the first source, the first drain, the first channel, the first gate dielectric, and the first gate. A first handle well is defined within the handle layer directly underlying the first channel and the buried insulator layer.

公开(公告)号：US09911867B2

公开(公告)日：2018-03-06

申请号：US15200347

申请日：2016-07-01

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Ming-Tsang Tsai ,  Khee Yong Lim ,  Kiok Boone Elgin Quek

IPC: H01L29/788 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7887 ,  H01L29/0653 ,  H01L29/42328 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/7851

Abstract: Integrated circuits, nonvolatile memory (NVM) structures, and methods for fabricating integrated circuits with NVM structures are provided. An exemplary integrated circuit includes a substrate and a dual-bit NVM structure overlying the substrate. The dual-bit NVM structure includes primary, first adjacent and second adjacent fin structures laterally extending in parallel over the substrate. The primary fin structure includes source, channel and drain regions. Each adjacent fin structure includes a program/erase gate. The dual-bit NVM structure further includes a first floating gate located between the channel region of the primary fin structure and the first adjacent fin structure and a second floating gate located between the channel region of the primary fin structure and the second adjacent fin structure. Also, the dual-bit NVM structure includes a control gate adjacent the primary fin structure.

公开(公告)号：US20180006158A1

公开(公告)日：2018-01-04

申请号：US15200347

申请日：2016-07-01

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Ming-Tsang Tsai ,  Khee Yong Lim ,  Kiok Boone Elgin Quek

IPC: H01L29/788 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7887 ,  H01L29/0653 ,  H01L29/42328 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/7851

Abstract: Integrated circuits, nonvolatile memory (NVM) structures, and methods for fabricating integrated circuits with NVM structures are provided. An exemplary integrated circuit includes a substrate and a dual-bit NVM structure overlying the substrate. The dual-bit NVM structure includes primary, first adjacent and second adjacent fin structures laterally extending in parallel over the substrate. The primary fin structure includes source, channel and drain regions. Each adjacent fin structure includes a program/erase gate. The dual-bit NVM structure further includes a first floating gate located between the channel region of the primary fin structure and the first adjacent fin structure and a second floating gate located between the channel region of the primary fin structure and the second adjacent fin structure. Also, the dual-bit NVM structure includes a control gate adjacent the primary fin structure.

公开(公告)号：US20170358692A1

公开(公告)日：2017-12-14

申请号：US15472625

申请日：2017-03-29

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Yuan Sun ,  Shyue Seng Tan ,  Kiok Boone Elgin Quek

IPC: H01L29/94 ,  H01L27/12 ,  H01L21/84 ,  H01L27/08 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/94 ,  H01L21/823475 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0811 ,  H01L27/1203 ,  H01L28/40 ,  H01L29/0688 ,  H01L29/66189

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate with an active layer overlying a buried insulator layer that in turn overlies a handle layer, where the active layer includes a first active well. A first source, a first drain, and a first channel are defined within the first active well, where the first channel is between the first source and the first drain. A first gate dielectric directly overlies the first channel, and a first gate directly overlies the first gate dielectric, where a first capacitor includes the first source, the first drain, the first channel, the first gate dielectric, and the first gate. A first handle well is defined within the handle layer directly underlying the first channel and the buried insulator layer.

公开(公告)号：US09734882B2

公开(公告)日：2017-08-15

申请号：US15012813

申请日：2016-02-01

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat Toh ,  Vinayak Bharat Naik ,  Kiok Boone Elgin Quek

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02 ,  G11C11/15

CPC classification number: G11C11/165 ,  G11C11/15 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1657 ,  G11C11/1659 ,  H01L27/228 ,  H01L43/02

Abstract: Memory cells and methods of forming thereof are disclosed. The memory cell includes a substrate and first and second select transistors. The first select transistor serves as a write selector and the second select transistor serves as a read selector. The gate of first select transistor is coupled to a write wordline (WL_w) and the gate of the second select transistor is coupled to a read/write wordline (WL_r/w). The source regions of the first and second select transistors are coupled to a source line (SL). A body well is disposed in the substrate. The body well serves as a body of the first and second select transistors. A back bias is applied to the body of the select transistors. A storage element which includes a magnetic tunnel junction (MTJ) element is coupled with a bitline (BL) and the first and the second select transistors.