公开(公告)号：US20200227335A1

公开(公告)日：2020-07-16

申请号：US16639545

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Feras EID ,  Johanna M. SWAN ,  Sergio CHAN ARGUEDAS ,  John J. BEATTY

IPC: H01L23/367 ,  H01L21/48 ,  H01L49/02

Abstract: A device package and a method of forming a device package are described. The device package has dies disposed on a substrate, and one or more layers with a high thermal conductivity, referred to as the highly-conductive (HC) intermediate layers, disposed on the dies on the substrate. The device package further includes a lid with legs on an outer periphery of the lid, a top surface, and a bottom surface. The legs of the lid are attached to the substrate with a sealant. The bottom surface of the lid is disposed over the one or more HC intermediate layers and the one or more dies on the substrate. The device package may also include thermal interface materials (TIMs) disposed on the HC intermediate layers. The TIMs may be disposed between the bottom surface of the lid and one or more top surfaces of the HC intermediate layers.

公开(公告)号：US20200098661A1

公开(公告)日：2020-03-26

申请号：US16139401

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Kelly LOFGREEN ,  Chia-Pin CHIU ,  Joseph PETRINI ,  Edvin CETEGEN ,  Betsegaw GEBREHIWOT ,  Feras EID

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/367

Abstract: Embodiments include an electronic system and methods of forming an electronic system. In an embodiment, the electronic system may include a package substrate and a die coupled to the package substrate. In an embodiment, the electronic system may also include an integrated heat spreader (IHS) that is coupled to the package substrate. In an embodiment the electronic system may further comprise a thermal interface pad between the IHS and the die. In an embodiment the die is thermally coupled to the IHS by a liquid metal thermal interface material (TIM) that contacts the thermal interface pad.

公开(公告)号：US20200075491A1

公开(公告)日：2020-03-05

申请号：US16611841

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Georgios C. DOGIAMIS ,  Feras EID ,  Thomas L. SOUNART ,  Aleksandar ALEKSOV ,  Johanna M. SWAN

IPC: H01L23/538 ,  H01L23/64 ,  H01G7/06 ,  H01L27/01

Abstract: Embodiments of the invention include a microelectronic device that includes a plurality of organic dielectric layers and a tunable ferroelectric capacitor formed in-situ with at least one organic dielectric layer of the plurality of organic dielectric layers. The tunable ferroelectric capacitor (e.g., varactor) includes first and second conductive electrodes and a ferroelectric layer that is positioned between the first and second conductive electrodes.

公开(公告)号：US20200066655A1

公开(公告)日：2020-02-27

申请号：US16611830

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Feras EID ,  Venkata Suresh R. GUTHIKONDA ,  Shankar DEVASENATHIPATHY ,  Chandra M. JHA ,  Je-Young CHANG ,  Kyle YAZZIE ,  Prasanna RAGHAVAN ,  Pramod MALATKAR

IPC: H01L23/00 ,  H01L23/544 ,  H05K1/02 ,  H05K1/18 ,  H01L25/065 ,  H01L21/50

Abstract: A foundation layer having a stiffener and methods of forming a stiffener are described. One or more dies are formed over the foundation layer. Each die has a front side surface that is electrically coupled to the foundation layer and a back side surface that is opposite from the front side surface. A stiffening layer (or a stiffener) is formed on the back side surface of at least one of the dies. The stiffening layer may be directly coupled to the back side surface of the one or more dies without an adhesive layer. The stiffening layer may include one or more materials, including at least one of a metal, a metal alloy, and a ceramic. The stiffening layer may be formed to reduce warpage based on the foundation layer and the dies. The one or more materials of the stiffening layer can be formed using a cold spray.

公开(公告)号：US20190297975A1

公开(公告)日：2019-10-03

申请号：US16303386

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Sasha N. OSTER ,  Feras EID ,  Shawna M. LIFF ,  Thomas L. SOUNART ,  Johanna M. SWAN ,  Baris BICEN ,  Valluri R. RAO

IPC: A41D27/28 ,  A41D13/00 ,  A41D27/24 ,  A61M35/00 ,  A61M5/145

Abstract: Embodiments of the invention include an active venting system. According to an embodiment of the invention, the active venting system may include a substrate having one or more seams formed through the substrate. In order to open the vents defined by the seams through the substrate, a piezoelectric layer may be formed proximate to one or more of the seams. Additional embodiments may include a first electrode and a second electrode that contact the piezoelectric layer in order to provide a voltage differential across the piezoelectric layer. In an embodiment the active venting system may be integrated into a garment. In such an embodiment, the garment may also include an electronics module for controlling the actuators. Additionally, conductive traces may be printed on the garment or sewn into the garment to provide electrical connections from the electronics module to each of the piezoelectric actuators.

公开(公告)号：US20190169020A1

公开(公告)日：2019-06-06

申请号：US15832223

申请日：2017-12-05

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Kristof DARMAWIKARTA ,  Robert A. MAY ,  Changhua LIU ,  Hiroki TANAKA ,  Feras EID

IPC: B81B7/02 ,  B81C1/00 ,  H01L23/498

Abstract: A package substrate is provided which comprises: one or more first conductive contacts on a first surface; one or more second conductive contacts on a second surface opposite the first surface; a dielectric layer between the first and the second surfaces; and an embedded sensing or actuating element on the dielectric layer conductively coupled with one of the first conductive contacts, wherein the embedded sensing or actuating element comprises a fixed metal layer in the dielectric layer and a flexible metal layer suspended over the fixed metal layer by one or more metal supports on the dielectric layer. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190141456A1

公开(公告)日：2019-05-09

申请号：US16096568

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Georgios C. DOGIAMIS ,  Feras EID ,  Adel A. ELSHERBINI ,  Johanna SWAN ,  Shawna M. LIFF ,  Thomas L. SOUNART ,  Sasha N. OSTER

IPC: H04R17/00 ,  B06B1/06

CPC classification number: H04R17/005 ,  B06B1/0622 ,  B06B1/0625 ,  B06B1/0644 ,  H04R2201/028

Abstract: Embodiments of the invention include an acoustic transducer device having a base structure that is positioned in proximity to a cavity of an organic substrate, a piezoelectric material in contact with a first electrode of the base structure, and a second electrode in contact with the piezoelectric material. In one example, for a transmit mode, a voltage signal is applied between the first and second electrodes and this causes a stress in the piezoelectric material which causes a stack that is formed with the first electrode, the piezoelectric material, and the second electrode to vibrate and hence the base structure to vibrate and generate acoustic waves.

公开(公告)号：US20190006282A1

公开(公告)日：2019-01-03

申请号：US15639870

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Feras EID

IPC: H01L23/538 ,  H01L23/498 ,  H01H85/08 ,  G06F1/16

Abstract: Embodiments of the invention include a microelectronic device that includes a plurality of organic dielectric layers, a cavity formed in at least one organic dielectric layer of the plurality of organic dielectric layers and a modular structure having first and second ports and a conductive member that is formed within the cavity. The conductive member provides modularity by being capable of connecting the first and second ports and also disconnecting the first and second ports.

公开(公告)号：US20180331003A1

公开(公告)日：2018-11-15

申请号：US15776755

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Krishna BHARATH ,  Mathew J. MANUSHAROW ,  Adel A. ELSHERBINI ,  Mihir K. ROY ,  Aleksandar ALEKSOV ,  Yidnekachew S. MEKONNEN ,  Javier SOTO GONZALEZ ,  Feras EID ,  Suddhasattwa NAD ,  Meizi JIAO

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/12 ,  H01L21/486 ,  H01L23/48 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.

公开(公告)号：US20180288868A1

公开(公告)日：2018-10-04

申请号：US15997644

申请日：2018-06-04

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Matthew MANUSHAROW ,  Krishna BHARATH ,  Zhichao ZHANG ,  Yidnekachew S. MEKONNEN ,  Aleksandar ALEKSOV ,  Henning BRAUNISCH ,  Feras EID ,  Javier SOTO

IPC: H05K1/02 ,  H01P3/08 ,  H01P3/02

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.