公开(公告)号：US20210265278A1

公开(公告)日：2021-08-26

申请号：US16799448

申请日：2020-02-24

Applicant: Intel Corporation

Inventor： Sung-Taeg Kang ,  Pranav Kalavade ,  Owen W. Jungroth ,  Prasanna Srinivasan

IPC: H01L23/532 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768 ,  H01L21/3205

Abstract: Apparatus, systems, or methods for a memory array having a plurality of word lines. A word line includes at least one word line plate, and the word line plate comprises a first material with a first resistivity. An edge of the word line plate is recessed and filled with a second material having a second resistivity that is lower than the first resistivity. As a result, the total resistance of the word line may be reduced compared to a word line using only the first material with the first resistivity. Other embodiments may also be described and claimed.

公开(公告)号：US10699790B2

公开(公告)日：2020-06-30

申请号：US16412269

申请日：2019-05-14

Applicant: Intel Corporation

Inventor： Krishna K. Parat ,  Pranav Kalavade ,  Koichi Kawai ,  Akira Goda

IPC: G11C16/04 ,  G11C16/16 ,  G11C8/12 ,  G11C16/34

Abstract: Methods, and apparatuses to erase and or soft program a block of NAND memory may include performing an erase cycle on a block of NAND memory comprising two or more sub-blocks, verifying the two or more sub-blocks until a sub-block fails to verify, stopping the verification in response to the failed verify, performing another erase cycle on the block of NAND memory, and re-starting to verify the two or more sub-blocks at the sub-block that failed to verify.

公开(公告)号：US10658053B2

公开(公告)日：2020-05-19

申请号：US15715980

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Neal R. Mielke ,  Krishna K. Parat ,  Shyam Sunder Raghunathan

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/08

Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.

公开(公告)号：US20190332277A1

公开(公告)日：2019-10-31

申请号：US16376283

申请日：2019-04-05

Applicant: Intel Corporation

Inventor： Anand S. Ramalingam ,  Pranav Kalavade

IPC: G06F3/06 ,  G06F12/02

Abstract: Systems, apparatuses and methods may provide for technology that reads a lower page, one or more intermediate pages and a last page from a set of multi-level non-volatile memory (NVM) cells, wherein one or more of a lower read time associated with the lower page or a last read time associated with the last page is substantially similar to an intermediate read time associated with the one or more intermediate pages.

公开(公告)号：US10303571B2

公开(公告)日：2019-05-28

申请号：US14932870

申请日：2015-11-04

Applicant: Intel Corporation

Inventor： Ning Wu ,  Xin Guo ,  Ramkarthik Ganesan ,  Pranav Kalavade ,  Robert Frickey

IPC: G06F11/00 ,  G06F11/20 ,  G06F12/02 ,  G06F11/14 ,  G06F12/0804 ,  G06F12/0868

Abstract: Technology for an apparatus is described. The apparatus can include a first non-volatile memory, a second non-volatile memory to have a write access time faster than the first non-volatile memory, and a memory controller. The memory controller can be configured to detect corrupted data in a selected data region in the first non-volatile memory. The selected data region can be associated with an increased risk of data corruption after data is written from the second non-volatile memory to the first non-volatile memory. Uncorrupted data in the second non-volatile memory that corresponds to the corrupted data in the first non-volatile memory can be identified. Data recovery in the first non-volatile memory can be performed by replacing the corrupted data in the first non-volatile memory with uncorrupted data from the second non-volatile memory.

公开(公告)号：US10290356B2

公开(公告)日：2019-05-14

申请号：US15050871

申请日：2016-02-23

Applicant: Intel Corporation

Inventor： Krishna K. Parat ,  Pranav Kalavade ,  Koichi Kawai ,  Akira Goda

IPC: G11C16/04 ,  G11C16/16 ,  G11C8/12 ,  G11C16/34

Abstract: Methods, and apparatuses to erase and or soft program a block of NAND memory may include performing an erase cycle on a block of NAND memory comprising two or more sub-blocks, verifying the two or more sub-blocks until a sub-block fails to verify, stopping the verification in response to the failed verify, performing another erase cycle on the block of NAND memory, and re-starting to verify the two or more sub-blocks at the sub-block that failed to verify.

公开(公告)号：US10289313B2

公开(公告)日：2019-05-14

申请号：US15195452

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Han Liu ,  Shantanu R. Rajwade ,  Pranav Kalavade

IPC: G06F1/24 ,  G06F3/06 ,  G11C11/56 ,  G11C7/06 ,  G11C16/04 ,  G11C16/08 ,  G11C16/32

Abstract: In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory. The storage device is to receive a read request from a computing host; identify a plurality of pages specified by the read request that are stored in the same group of memory cells of the NAND flash memory, wherein each memory cell of the group of memory cells is to store a bit of each of the plurality of identified pages; and read, in a single read cycle, the plurality of pages from the group of memory cells of the NAND flash memory.

公开(公告)号：US10275156B2

公开(公告)日：2019-04-30

申请号：US15280725

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Anand S. Ramalingam ,  Jawad B. Khan ,  Pranav Kalavade

IPC: G06F3/06 ,  G11C16/16 ,  G11C16/34 ,  G11C16/04

Abstract: Systems, apparatuses and methods may provide for initiating an erase of a block of non-volatile memory in response to an erase command, wherein the block includes a plurality of sub-blocks. Additionally, a failure of the erase with respect to a first subset of the plurality of sub-blocks may be tracked on an individual sub-block basis, wherein the erase is successful with respect to a second subset of the plurality of sub-blocks. In one example, use of the second subset of the plurality of sub-blocks is permitted, whereas use of the first subset of the plurality of sub-blocks is prevented.

公开(公告)号：US10254977B2

公开(公告)日：2019-04-09

申请号：US15803107

申请日：2017-11-03

Applicant: Intel Corporation

Inventor： Anand S. Ramalingam ,  Pranav Kalavade

IPC: G11C7/00 ,  G06F3/06 ,  G06F12/02

Abstract: Systems, apparatuses and methods may provide for technology that reads a lower page, one or more intermediate pages and a last page from a set of multi-level non-volatile memory (NVM) cells, wherein one or more of a lower read time associated with the lower page or a last read time associated with the last page is substantially similar to an intermediate read time associated with the one or more intermediate pages.

公开(公告)号：US10242734B1

公开(公告)日：2019-03-26

申请号：US15720492

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Ali Khakifirooz ,  Rohit S. Shenoy ,  Pranav Kalavade ,  Aliasgar S. Madraswala ,  Yogesh B. Wakchaure

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/34 ,  G11C7/10

Abstract: Provided are techniques for resuming storage die programming after power loss. In response to receipt of an indication of the power loss, data that was to be programmed to multi-level cell NAND blocks are copied to single level cell NAND blocks and a pulse number at which programming was interrupted is stored. In response to receipt of an indication to resume from the power loss, the data is copied from the single level cell NAND blocks to a page buffer, the pulse number is retrieved, and programming of the multi-level cell NAND blocks is resumed at the retrieved pulse number using the data in the page buffer.