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    LOCAL POWER GATE (LPG) INTERFACES FOR POWER-AWARE OPERATIONS
    53.
    发明申请
    LOCAL POWER GATE (LPG) INTERFACES FOR POWER-AWARE OPERATIONS 审中-公开
    本地电力门（LPG）接口，用于功率操作

    公开(公告)号：US20170068298A1

    公开(公告)日：2017-03-09

    申请号：US15354018

    申请日：2016-11-17

    Applicant: INTEL CORPORATION

    Inventor： Michael Mishaeli ,  Ron Gabor ,  Robert C. Valentine ,  Alex Gerber ,  Zeev Sperber

    IPC: G06F1/32

    CPC classification number: G06F1/3206 ,  G06F1/3287 ,  G06F9/22 ,  Y02D10/171

    Abstract: Technologies for local power gate (LPG) interfaces for power-aware operations are described. A system on chip (SoC) includes a first functional unit, a second functional unit, and local power gate (LPG) hardware coupled to the first functional unit and the second functional unit. The LPG hardware is to power gate the first functional unit according to local power states of the LPG hardware. The second functional unit decodes a first instruction to perform a first power-aware operation of a specified length, including computing an execution code path for execution. The second functional unit monitors a current local power state of the LPG hardware, selects a code path based on the current local power state, the specified length, and a specified threshold, and issues a hint to the LPG hardware to power up the first functional unit and continues execution of the first power-aware operation without waiting for the first functional unit to be powered up.

    Abstract translation: 描述了用于功率感知操作的本地电源门（LPG）接口的技术。 片上系统（SoC）包括耦合到第一功能单元和第二功能单元的第一功能单元，第二功能单元和本地电源门（LPG）硬件。 LPG硬件根据LPG硬件的本地电源状态为第一个功能单元供电。 第二功能单元解码执行指定长度的第一功率感知操作的第一指令，包括计算用于执行的执行代码路径。 第二功能单元监视LPG硬件的当前本地电源状态，根据当前本地电源状态，指定长度和指定的阈值选择代码路径，并向LPG硬件发出提示，以启动第一个功能 并且继续执行第一功率感知操作，而不等待第一功能单元被加电。

    MULTIPLE CHUNK SUPPORT FOR MEMORY CORRUPTION DETECTION ARCHITECTURES
    54.
    发明申请
    MULTIPLE CHUNK SUPPORT FOR MEMORY CORRUPTION DETECTION ARCHITECTURES 有权
    用于存储器腐蚀检测架构的多重CHUNK支持

    公开(公告)号：US20160371179A1

    公开(公告)日：2016-12-22

    申请号：US14746702

    申请日：2015-06-22

    Applicant: Intel Corporation

    Inventor： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman

    IPC: G06F12/02

    CPC classification number: G06F12/023 ,  G06F11/0775 ,  G06F11/1004 ,  G06F11/1076 ,  G06F2212/1044

    Abstract: Memory corruption detection technologies are described. An example processing system includes a processing core including a register to store an address of a memory corruption detection (MCD) table. The processing core can allocate a memory block of pre-determined size and can allocate a plurality of buffers within the memory block using a memory metadata word stored in an entry of the MCD table. The memory metadata word can include metadata that can identify a first bit range within the memory block for a first buffer and a second bit range within the memory block for a second buffer

    Abstract translation: 描述了内存损坏检测技术。 示例性处理系统包括处理核心，其包括用于存储存储器损坏检测（MCD）表的地址的寄存器。 处理核心可以分配预定大小的存储器块，并且可以使用存储在MCD表的条目中的存储器元数据字来在存储块内分配多个缓冲器。 存储器元数据字可以包括可识别第一缓冲器的存储器块内的第一位范围的元数据和用于第二缓冲器的存储器块内的第二位范围

    Method and apparatus to protect a processor against excessive power usage
    55.
    发明授权
    Method and apparatus to protect a processor against excessive power usage 有权
    防止处理器过度使用电力的方法和装置

    公开(公告)号：US09292362B2

    公开(公告)日：2016-03-22

    申请号：US13926089

    申请日：2013-06-25

    Applicant: Intel Corporation

    Inventor： Lev Makovsky ,  Zeev Sperber ,  Efraim Rotem ,  Nir Rosenzweig ,  Stanislav Shwartsman ,  Raanan Sade ,  Igor Yanover ,  Gavri Berger ,  Tomer Weiner ,  Ron Gabor

    IPC: G06F1/04 ,  G06F9/54 ,  G06F9/30 ,  G06F9/48 ,  G06F1/32

    CPC classification number: G06F9/542 ,  G06F1/3206 ,  G06F9/30 ,  G06F9/4856 ,  Y02D10/24 ,  Y02D10/32

    Abstract: In an embodiment, a processor includes at least a first core. The first core includes execution logic to execute operations, and a first event counter to determine a first event count associated with events of a first type that have occurred since a start of a first defined interval. The first core also includes a second event counter to determine a second event count associated with events of a second type that have occurred since the start of the first defined interval, and stall logic to stall execution of operations including at least first operations associated with events of the first type, until the first defined interval is expired responsive to the first event count exceeding a first combination threshold concurrently with the second event count exceeding a second combination threshold. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器至少包括第一核。 第一核心包括执行操作的执行逻辑，以及第一事件计数器，用于确定与自第一定义间隔开始以来已经发生的第一类型的事件相关联的第一事件计数。 第一核心还包括第二事件计数器，用于确定与自第一定义间隔开始以来已经发生的第二类型的事件相关联的第二事件计数，以及停止逻辑以停止包括至少与事件相关联的第一操作的操作的执行 直到第一定义间隔响应于超过第一组合阈值的第一事件计数而超过第二事件计数超过第二组合阈值。 描述和要求保护其他实施例。

    Memory tagging metadata manipulation
    58.
    发明授权
    Memory tagging metadata manipulation 有权

    公开(公告)号：US11656998B2

    公开(公告)日：2023-05-23

    申请号：US16729371

    申请日：2019-12-28

    Applicant: Intel Corporation

    Inventor： Ron Gabor ,  Enrico Perla ,  Raanan Sade ,  Igor Yanover ,  Tomer Stark

    IPC: G06F12/00 ,  G06F12/0895 ,  G06F12/1009 ,  G06F12/1045 ,  G06F12/14

    CPC classification number: G06F12/0895 ,  G06F12/1009 ,  G06F12/1054 ,  G06F12/1441 ,  G06F2212/7207 ,  G06F2212/7209

    Abstract: An apparatus and method for tagged memory management, an embodiment including execution circuitry to generate a system memory access request having a first address pointer and address translation circuitry to determine whether to translate the first address pointer with metadata processing. The address translation circuitry is to access address translation tables to translate the first address pointer to a first physical address, perform a lookup in a memory metadata table to identify a memory metadata value associated with a physical address range including the first physical address, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value; and when the comparison results in a validation of the memory access request, then return the first physical address.

    MEMORY PROTECTION WITH HIDDEN INLINE METADATA
    59.
    发明申请
    MEMORY PROTECTION WITH HIDDEN INLINE METADATA 有权

    公开(公告)号：US20220222186A1

    公开(公告)日：2022-07-14

    申请号：US17705857

    申请日：2022-03-28

    Applicant: Intel Corporation

    Inventor： David M. Durham ,  Ron Gabor

    IPC: G06F12/14 ,  G06F21/60 ,  G06F21/62 ,  G06F21/57

    Abstract: Embodiments are directed to memory protection with hidden inline metadata. An embodiment of an apparatus includes processor cores; a computer memory for the storage of data; and cache memory communicatively coupled with one or more of the processor cores, wherein one or more processor cores of the plurality of processor cores are to implant hidden inline metadata in one or more cachelines for the cache memory, the hidden inline metadata being hidden at a linear address level.

    APPARATUSES, METHODS, AND SYSTEMS FOR SELECTIVE LINEAR ADDRESS MASKING BASED ON PROCESSOR PRIVILEGE LEVEL AND CONTROL REGISTER BITS
    60.
    发明申请
    APPARATUSES, METHODS, AND SYSTEMS FOR SELECTIVE LINEAR ADDRESS MASKING BASED ON PROCESSOR PRIVILEGE LEVEL AND CONTROL REGISTER BITS 有权

    公开(公告)号：US20210209023A1

    公开(公告)日：2021-07-08

    申请号：US17146440

    申请日：2021-01-11

    Applicant: Intel Corporation

    Inventor： Ron Gabor ,  Igor Yanover

    IPC: G06F12/0811 ,  G06F9/30 ,  G06F9/34

    Abstract: Systems, methods, and apparatuses relating to linear address masking architecture are described. In one embodiment, a hardware processor includes an address generation unit to generate a linear address for a memory access request to a memory, at least one control register comprising a user mode masking bit and a supervisor mode masking bit, a register comprising a current privilege level indication, and a memory management unit to mask out a proper subset of bits inside an address space of the linear address for the memory access request based on the current privilege level indication and either of the user mode masking bit or the supervisor mode masking bit to produce a resultant linear address, and output the resultant linear address.

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