公开(公告)号：US20210305494A1

公开(公告)日：2021-09-30

申请号：US16828489

申请日：2020-03-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  Chih-Chao Yang ,  Michael Rizzolo ,  Theodorus E. Standaert

IPC: H01L43/02 ,  H01L43/12 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34

Abstract: A semiconductor device includes a base structure of an embedded memory device including a bottom electrode contact (BEC) landing pad within a memory area of the embedded memory device and a first metallization level having at least a first conductive line within a logic area of the embedded memory device, a cap layer disposed on the base structure, a BEC disposed through the cap layer on the BEC landing pad, a memory pillar disposed on the BEC and the cap layer, encapsulation layers encapsulating the memory pillar to protect the memory stack, and a second metallization level including a second conductive line surrounding the top electrode, a via disposed on the first conductive line such that the second via is below the top electrode, and a third conductive line disposed on the via to enable the memory pillar to be fitted between the first and second metallization levels.

公开(公告)号：US20210296169A1

公开(公告)日：2021-09-23

申请号：US16826944

申请日：2020-03-23

Applicant: International Business Machines Corporation

Inventor： Timothy Mathew Philip ,  Sagarika Mukesh ,  Dominik Metzler ,  Ashim Dutta ,  John Christopher Arnold

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: A method includes forming a plurality of elongated dielectric members on a semiconductor substrate. The elongated dielectric members each extend vertically from the semiconductor substrate and define opposed vertical walls. The method further includes forming opposed spacer walls on the vertical walls of the elongated dielectric members. Adjacent spacer walls of longitudinally adjacent elongated dielectric members define first trenches therebetween. The method also includes depositing a first metal material within the first trenches to form a first set of first metal lines, removing the elongated dielectric members to define second trenches between the opposed spacer wails on the opposed vertical wails of each elongated dielectric member, and depositing a second metal material within the second trenches to form a second set of second metal lines. The first and second metal lines of the first and second sets are disposed in alternating arrangement.

公开(公告)号：US11081643B1

公开(公告)日：2021-08-03

申请号：US16748738

申请日：2020-01-21

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Saba Zare ,  Michael Rizzolo ,  Theodorus E. Standaert ,  Daniel C. Edelstein

IPC: H01L43/12 ,  H01L27/22

Abstract: Form a metallized layer at a top surface of a semiconductor wafer. The metallized layer includes a bottom contact and a dielectric barrier surrounding the bottom contact. Deposit a memory stack layer onto the metallized layer. The memory stack layer forms a first overspill on a bevel of the wafer. Remove the first overspill from the bevel using a first high-angle ion beam during a cleanup etch.

公开(公告)号：US11062946B2

公开(公告)日：2021-07-13

申请号：US16183787

申请日：2018-11-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  Jennifer Church ,  Ekmini A. de Silva ,  Luciana M. Thompson

IPC: H01L21/768 ,  H01L21/311 ,  H01L29/78 ,  H01L29/66 ,  H01L21/321

Abstract: A method for forming one or more self-aligned contacts on a semiconductor device includes applying a protective layer on an oxide surface above a source and drain of the semiconductor device. The protective layer covers a top surface of the oxide surface selective to nitride above a gate contact pillar. A sacrificial layer is applied to the nitride surface. The sacrificial layer is deposited only on the nitride surface that is selective to the oxide layer coated with the protective layer. The protective layer is removed from the oxide surface and source/drain contact holes are etched in the oxide surface to form self-aligned contacts on the semiconductor device.

公开(公告)号：US20210125865A1

公开(公告)日：2021-04-29

申请号：US16664830

申请日：2019-10-26

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  John Arnold ,  Dominik Metzler

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/522 ,  H01L23/532

Abstract: Techniques for self-aligned top via formation at line ends are provided. In one aspect, a method of forming self-aligned vias at line ends includes: patterning (even/odd) metal lines including using a (first/second) hardmask; cutting the hardmask and a select metal line, even or odd, using a cut mask having a window that exposes the hardmask over a cut region of the select metal line; enlarging the window to expose the hardmask on either side of the cut region; selectively etching the hardmask using the enlarged window to form a T-shaped cavity within the cut region; filling the T-shaped cavity with a gap fill dielectric; removing the hardmask; and recessing the metal lines, wherein the gap fill dielectric overhangs portions of the select metal line that, by the recessing, form the self-aligned vias at ends of the metal lines. A structure is also provided.

公开(公告)号：US10685879B1

公开(公告)日：2020-06-16

申请号：US16541873

申请日：2019-08-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John C. Arnold ,  Ashim Dutta ,  Dominik Metzler ,  Takeshi Nogami

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: A method for fabricating a semiconductor device includes forming misalignment tolerant vias each having a landing area configured to account for alignment mismatch resulting from subsequent formation of conductive structures, depositing a conductive layer over the misalignment tolerant vias, and obtaining conductive layer patterning including each of the conductive structures formed on at least a portion of a respective one of the landing areas, including subtractively patterning the conductive layer. The misalignment tolerant vias and the conductive structures imparting a semiconductor device geometry accounting for the alignment mismatch.

公开(公告)号：US20190258171A1

公开(公告)日：2019-08-22

申请号：US15902036

申请日：2018-02-22

Applicant: International Business Machines Corporation

Inventor： Luciana Meli Thompson ,  Ashim Dutta ,  Ekmini A. De Silva

IPC: G03F7/20 ,  C23C16/455 ,  G03F7/16 ,  C23C16/24 ,  C23C16/40 ,  H01L21/027 ,  H01L21/02 ,  H01L21/66

Abstract: Methods for post-lithographic inspection using an e-beam inspection tool of organic EUV sensitive photoresists generally includes conformal deposition of a silicon derivative or a metal oxide onto the relief image, wherein the silicon derivative is a material selected to have a dielectric constant that is greater than the dielectric constant of the underlying organic EUV sensitive photoresist. The conformal deposition of the silicon derivative or the metal oxide includes a low temperature vapor deposition process of less than about 100° C. to provide a coating thickness of less than about 5 nanometers.

公开(公告)号：US12277960B2

公开(公告)日：2025-04-15

申请号：US17644349

申请日：2021-12-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  Dominik Metzler ,  Oscar van der Straten ,  Theodorus E. Standaert

IPC: H01L23/00 ,  G11C11/00 ,  G11C11/16 ,  H01L23/522 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A memory device with modified top electrode contact includes a memory pillar composed of a bottom electrode, a magnetic random-access memory (MRAM) stack above the bottom electrode, and a top electrode above the MRAM stack. A first portion of an encapsulation layer is disposed along opposite sidewalls of the bottom electrode, on opposite sidewalls of the MRAM stack and on opposite sidewalls of a bottom portion of the top electrode, a second portion of the encapsulation layer is located above a second dielectric layer. A metal cap is located above an uppermost surface and opposite sidewalls of a top portion of the top electrode and above an uppermost surface of the first portion of the encapsulation layer. A second conductive interconnect is formed above a top surface of the metal cap wrapping around opposite sidewalls of the first portion of the encapsulation layer and opposite sidewalls of the metal cap.

公开(公告)号：US20250113498A1

公开(公告)日：2025-04-03

申请号：US18479452

申请日：2023-10-02

Applicant: International Business Machines Corporation

Inventor： Shravana Kumar Katakam ,  Ashim Dutta ,  Chih-Chao Yang

IPC: H01G4/012 ,  H01G4/08 ,  H01G4/33

Abstract: A metal-insulator-metal (MIM) capacitor includes a dielectric layer forming a plane and a capacitor dielectric formed in a pattern having a width parallel to the plane and a height transverse to the plane. Electrodes are formed as sidewall spacers on opposite sides of the width of the capacitor dielectric. Each of the electrodes has a contact to make an electrical connection to the electrode, the contact being disposed within the height.

公开(公告)号：US20250096122A1

公开(公告)日：2025-03-20

申请号：US18467755

申请日：2023-09-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  Chih-Chao Yang ,  Oscar van der Straten ,  Shravana Kumar Katakam

IPC: H01L23/525 ,  H01L23/522

Abstract: A semiconductor structure including a metal sidewall spacer arranged on a vertical sidewall of a dielectric pedestal, a fuse dielectric layer on top of the dielectric pedestal, and a conductive element on top of the fuse dielectric layer and directly above the metal sidewall spacer.