公开(公告)号：US20200083221A1

公开(公告)日：2020-03-12

申请号：US16688222

申请日：2019-11-19

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Jingyun Zhang ,  Choonghyun Lee ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/092 ,  H01L21/02 ,  H01L29/49 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/8238

Abstract: Embodiments of the invention are directed to a configuration of nanosheet FET devices in a first region of a substrate. Each of the nanosheet FET devices in the first region includes a first channel nanosheet, a second channel nanosheet over the first channel nanosheet, a first gate structure around the first channel nanosheet, and a second gate structure around the second channel nanosheet, wherein the first gate structure and the second gate structure pinch off in a pinch off area between the first gate structure and the second gate structure. The first gate structure includes a doped region, and the second gate structure includes a doped region. At least a portion of the pinch off area is undoped.

公开(公告)号：US20200066839A1

公开(公告)日：2020-02-27

申请号：US16108567

申请日：2018-08-22

Applicant: International Business Machines Corporation

Inventor： Jingyun Zhang ,  Alexander Reznicek ,  Choonghyun Lee ,  Xin Miao

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8234

Abstract: An I/O device nanosheet material stack of suspended semiconductor channel material nanosheet is provided above a semiconductor substrate. A physically exposed portion of each suspended semiconductor channel material nanosheet is thinned to increase the inter-nanosheet spacing between each vertically stacked semiconductor channel material nanosheet. An I/O device functional gate structure is formed wrapping around the thinned portion of each suspended semiconductor channel material nanosheet.

公开(公告)号：US10573723B1

公开(公告)日：2020-02-25

申请号：US16110785

申请日：2018-08-23

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Choonghyun Lee ,  SangHoon Shin ,  Jingyun Zhang ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/51 ,  H01L27/092 ,  H01L29/786 ,  H01L21/8238

Abstract: Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by forming a gradient threshold voltage adjusting gate dielectric structure between the bottom drain region of the FET and the top source region of the FET. The gradient threshold voltage adjusting gate dielectric structure includes a doped interface high-k gate dielectric material that is located in proximity to the bottom drain region and a non-doped high-k dielectric material that is located in proximity to the top source region. The non-doped high-k dielectric material has a higher threshold voltage than the doped interface high-k gate dielectric.

公开(公告)号：US20200058767A1

公开(公告)日：2020-02-20

申请号：US16105442

申请日：2018-08-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Juntao Li ,  Choonghyun Lee ,  Shogo Mochizuki

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08

Abstract: A method of forming a fin field effect transistor device is provided. The method includes forming a plurality of vertical fins on a substrate. The method further includes forming a bottom source/drain layer adjacent to the plurality of vertical fins, and growing a doped layer on the bottom source/drain layer and sidewalls of the plurality of vertical fins. The method further includes forming a dummy gate liner on the doped layer and the bottom source/drain layer, and forming a dummy gate fill on the dummy gate liner. The method further includes forming a protective cap layer on the dummy gate fill, and removing a portion of the protective cap layer to expose a top surface of the plurality of vertical fins.

公开(公告)号：US20200058565A1

公开(公告)日：2020-02-20

申请号：US16105690

申请日：2018-08-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Juntao Li ,  Choonghyun Lee

IPC: H01L21/8238 ,  H01L21/225 ,  H01L21/306 ,  H01L21/324 ,  H01L29/66 ,  H01L23/535 ,  H01L27/092 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78

Abstract: A method of forming a fin field effect transistor circuit is provided. The method includes forming a plurality of vertical fins on a substrate, and forming a protective liner having a varying thickness on the substrate and plurality of vertical fins. The method further includes removing thinner portions of the protective liner from the substrate to form protective liner segments on the plurality of vertical fins. The method further includes removing portions of the substrate exposed by removing the thinner portions of the protective liner to form trenches adjacent to at least one pair of vertical fins and two substrate mesas. The method further includes laterally etching the substrate mesa to widen the trench, reduce the width of the substrate mesa to form a supporting pillar, and undercut the at least one pair of vertical fins, and forming a first bottom source/drain layer in the widened trench.

公开(公告)号：US10566251B2

公开(公告)日：2020-02-18

申请号：US16037993

申请日：2018-07-17

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Kangguo Cheng ,  Juntao Li

IPC: H01L21/84 ,  H01L29/786 ,  H01L29/66 ,  H01L29/49 ,  H01L21/3213 ,  H01L29/51 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/8234

Abstract: Techniques for reducing work function metal variability along the channel of VFET devices are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer; forming bottom source/drains at a base of the fins and bottom spacers on the bottom source/drains; forming gate stacks over the fins including a gate conductor having a combination of work function metals including an outer layer and at least one inner layer of the work function metals; isotropically etching the work function metals which recesses the gate stacks with an outwardly downward sloping profile; isotropically etching the at least one inner layer while covering the outer layer of the work function metals to eliminate the outwardly downward sloping profile of the gate stacks; forming top spacers above the gate stacks; and forming top source and drains at tops of the fins. A VTFET device is also provided.

公开(公告)号：US20200051979A1

公开(公告)日：2020-02-13

申请号：US16101659

申请日：2018-08-13

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Reinaldo Vega ,  Choonghyun Lee ,  Hari Mallela ,  Li-Wen Hung

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49

Abstract: Multi-voltage threshold vertical transport transistors and methods of fabrication generally include forming the transistors with vertically oriented silicon fin channels for both the n-type doped field effect transistors (nFET) and the p-type doped field effect transistors (pFET). A silicon oxynitride interfacial layer is provided on sidewalls of the fins in the nFET and a silicon dioxide interfacial with aluminum is provided on sidewalls of the fins in the pFET to provide an aluminum induced dipole. A high k dielectric overlays the interfacial layers and a common work function metal overlays the high k dielectric layer to define a gate structure.

公开(公告)号：US10559676B2

公开(公告)日：2020-02-11

申请号：US15960078

申请日：2018-04-23

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Choonghyun Lee ,  Jingyun Zhang ,  Pouya Hashemi

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/49

Abstract: VTFET devices having a differential top spacer are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer including NFET and PFET fins; forming bottom source and drains at a base of the NFET/PFET fins; forming bottom spacers on the bottom source and drains; forming gate stacks alongside the NFET/PFET fins that include a same workfunction metal on top of a gate dielectric; annealing the gate stacks which generates oxygen vacancies in the gate dielectric; forming top spacers that include an oxide spacer layer in contact with only the gate stacks alongside the PFET fins, wherein the oxide spacer layer supplies oxygen filling the oxygen vacancies in the gate dielectric only in the gate stacks alongside the PFET fins; and forming top source and drains above the gate stacks at the tops of the NFET/PFET fins. A VTFET device is also provided.

公开(公告)号：US20200044023A1

公开(公告)日：2020-02-06

申请号：US16050735

申请日：2018-07-31

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Choonghyun Lee ,  Xin Miao ,  Jingyun Zhang

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/8238 ,  H01L23/532 ,  H01L29/66 ,  H01L29/08

Abstract: Parasitic transistor formation under a semiconductor containing nanosheet device is eliminated by forming an airgap between the source/drain regions of the semiconductor containing nanosheet device and the semiconductor substrate. The airgap is created by forming a sacrificial germanium-containing semiconductor material at the bottom of the source/drain regions prior to the epitaxial growth of the source/drain regions from physically exposed sidewalls of each semiconductor channel material nanosheet of a nanosheet material stack. After inner dielectric spacer formation, the sacrificial germanium-containing semiconductor material can be reflown to seal any possible openings to the semiconductor substrate. The source/drain regions are then epitaxially grown and thereafter, the sacrificial germanium-containing semiconductor material is removed from the structure creating the airgap between the source/drain regions of the semiconductor containing nanosheet device and the semiconductor substrate.

公开(公告)号：US10553696B2

公开(公告)日：2020-02-04

申请号：US15819708

申请日：2017-11-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Pouya Hashemi ,  Choonghyun Lee ,  Alexander Reznicek ,  Jingyun Zhang

IPC: H01L29/49 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/764 ,  H01L21/768 ,  H01L21/28 ,  H01L29/66 ,  H01L27/092

Abstract: Semiconductor devices and method of forming the same include forming a stack of vertically aligned, alternating layers including sacrificial layers and channel layers. The sacrificial layers are recessed relative to the channel layers to form recesses. A dual-layer dielectric is deposited. The dual-layer dielectric includes a first dielectric material formed conformally on surfaces of the recesses and a second dielectric material filling a remainder of the recesses. The first dielectric material is recessed relative to the second dielectric material. The second dielectric material is etched away to create air gaps. Outer spacers are formed using a third dielectric material that pinches off, preventing the third dielectric material from filling the air gaps.