公开(公告)号：US09589958B1

公开(公告)日：2017-03-07

申请号：US15004063

申请日：2016-01-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sivananda K. Kanakasabapathy ,  Fee Li Lie ,  Eric Miller ,  Stuart A. Sieg

IPC: H01L21/00 ,  H01L27/092 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/3065 ,  H01L29/16 ,  H01L29/161 ,  H01L29/201 ,  H01L21/8252 ,  H01L21/311

CPC classification number: H01L27/0886 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/0924 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/201 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method is disclosed which cuts hard mask fins thinner than the target fin critical dimension and then enlarges the dimension of the fin hard mask critical dimension to meet the target fin critical dimension.

Abstract translation: 公开了一种切割比目标鳍关键尺寸更薄的硬掩模翅片的方法，然后扩大翅片硬掩模临界尺寸以满足目标鳍临界尺寸。

公开(公告)号：US20240421085A1

公开(公告)日：2024-12-19

申请号：US18210041

申请日：2023-06-14

Applicant: International Business Machines Corporation

Inventor： Tsung-Sheng Kang ,  Tao Li ,  Ruilong Xie ,  Eric Miller

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor structure includes a plurality of gate-all-around field effect transistors. Each of the gate-all-around field effect transistors includes first and second source-drain regions; at least one channel region interconnecting the first and second source-drain regions; and a gate structure surrounding the at least one channel region. A direct backside contact is located below one of the first and second source-drain regions. The direct backside contact has an upper portion. A dielectric liner is wrapped around the upper portion of the direct backside contact.

公开(公告)号：US20240222448A1

公开(公告)日：2024-07-04

申请号：US18148577

申请日：2022-12-30

Applicant: International Business Machines Corporation

Inventor： Eric Miller ,  Nelson Felix ,  Andrew Herbert Simon

IPC: H01L29/417 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/76831 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes first and second nanosheet stacks above an upper surface of a semiconductor substrate, a first source/drain on an end of the first nanosheet stack, and a second source/drain on an end of the second nanosheet stack. A first gate stack wraps around individual channels of the first nanosheet stack and a second gate stack wraps around individual channels the second nanosheet stack. An interlayer dielectric covers the first and second nanosheet stacks, the first and second source/drains, and the first and second gate stacks. The semiconductor device further includes a first source/drain contact that contacts the first source/drain and a second source/drain contact that contacts the second source/drain. The first and second source/drain contacts extend continuously from the first and second source/drains, respectively, to an upper surface of the interlayer dielectric.

公开(公告)号：US20240186401A1

公开(公告)日：2024-06-06

申请号：US18072840

申请日：2022-12-01

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Effendi Leobandung ,  Eric Miller

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/823821 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Semiconductor devices having separate (i.e., non-overlapping) gate all around replacement metal gates are provided. In one aspect, a semiconductor device includes: a wafer; and at least a first transistor of a first polarity (e.g., a pFET) and a second transistor of a second polarity (e.g., an nFET) on the wafer, where a gate electrode of the first transistor and a gate electrode of the second transistor have a single pair of vertically adjoining sidewalls. The workfunction-setting metals employed in the gate electrodes of the first and second transistors can vary, as can the composition, thickness, etc. of the gate dielectric that is present beneath the gate electrodes. A method of fabricating the present semiconductor devices is also provided.

公开(公告)号：US20230411477A1

公开(公告)日：2023-12-21

申请号：US17807873

申请日：2022-06-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Su Chen Fan ,  Nicolas Jean Loubet ,  Yann Mignot ,  Tsung-Sheng Kang ,  Eric Miller

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/45 ,  H01L29/417

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/41775 ,  H01L29/458 ,  H01L29/78696

Abstract: A gate-all-around transistor structure including a channel region surrounded on three sides by a gate conductor, and a pair of salicide regions extending from opposite ends of the channel region in a direction parallel with the gate conductor.

公开(公告)号：US20230369217A1

公开(公告)日：2023-11-16

申请号：US17662748

申请日：2022-05-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Nicholas Anthony Lanzillo ,  Julien Frougier ,  Kangguo Cheng ,  Eric Miller ,  Lawrence A. Clevenger ,  DANIEL JAMES DECHENE

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L23/5286 ,  H01L27/0922 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/66545 ,  H01L29/66742

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A first field-effect transistor (FET) having a first source/drain region is formed. A second FET having a second source/drain region is formed, where the second FET is stacked above the first FET. A trench extending from above the second source/drain region to beneath the first source/drain region is formed, where the trench passes through portions of (i) the first source/drain region and (ii) the second source/drain region. A bottom contact is formed in the trench. A dielectric layer is formed in the trench, the dielectric layer on a top surface of the bottom contact. A top contact is formed in the trench, the top contact on a top surface of the dielectric layer.

公开(公告)号：US11710768B2

公开(公告)日：2023-07-25

申请号：US17303275

申请日：2021-05-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Eric Miller ,  Indira Seshadri ,  Andrew M. Greene ,  Julien Frougier ,  Veeraraghavan S. Basker

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/0642 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: An apparatus including a substrate and a first nanosheet device located on the substrate. A second nanosheet device is located on the substrate, where the second nanosheet device is adjacent to the first nanosheet device. At least one first gate located on the first nanosheet device and the at least one first gate has a first width. At least one second gate located on the second nanosheet device and the at least one second gate has a second width. The first width and the second width are substantially the same. A diffusion break located between the first nanosheet device and the second nanosheet device. The diffusion break prevents the first nanosheet device from contacting the second nanosheet device, and the diffusion break has a third width. The third width is larger than the first width and the second width.

公开(公告)号：US11695059B2

公开(公告)日：2023-07-04

申请号：US17518649

申请日：2021-11-04

Applicant: International Business Machines Corporation

Inventor： Tao Li ,  Indira Seshadri ,  Nelson Felix ,  Eric Miller

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/66666 ,  H01L21/823814 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/7827

Abstract: A technique relates to a semiconductor device. A first epitaxial material is formed under a bottom surface of a set of fins, the first epitaxial material being under fin channel regions of the set of fins. A second epitaxial material is formed adjacent to the first epitaxial material and remote from the fin channel regions, a combination of the first epitaxial material and the second epitaxial material forming a bottom source or drain (source/drain) layer. A top source/drain layer is formed on an upper portion of the set of fins, gate material being disposed around the set of fins between the top source/drain layer and the bottom source/drain layer.

公开(公告)号：US20230139929A1

公开(公告)日：2023-05-04

申请号：US17512744

申请日：2021-10-28

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Stuart Sieg ,  Kevin Shawn Petrarca ,  Eric Miller

IPC: H01L23/48 ,  H01L29/66 ,  H01L29/06 ,  H01L27/12

Abstract: A semiconductor structure is provided in which a via to buried power rail (VBPR) contact structure is present that has a via portion contacting a buried power rail and a non-via portion contacting a source/drain region of a first functional gate structure present in a first device region. A dielectric spacer structure including a base dielectric spacer and a replacement dielectric spacer is located between the VPBR contact structure and the first functional gate structure. The replacement dielectric spacer is composed of a gate cut trench dielectric material that is also present in a gate cut trench that is located between the first functional gate structure present in the first device region, and a second functional gate structure that is present in a second device region. The replacement dielectric spacer replaces a damaged region of a dielectric spacer that is originally present during VBPR formation.

公开(公告)号：US20230095508A1

公开(公告)日：2023-03-30

申请号：US17491408

申请日：2021-09-30

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Indira Seshadri ,  Eric Miller ,  Kangguo Cheng

IPC: H01L29/417 ,  H01L29/40 ,  H01L27/092

Abstract: Embodiments disclosed herein include a semiconductor structure for reducing contact to contact shorting. The semiconductor structure may include a gate cut region with a liner and a dielectric core confined within a first lateral side of the liner and a second lateral side of the liner. The semiconductor structure may also include a first source/drain (S/D) contact overlapping the first lateral side and the dielectric core. The first S/D may include a line-end that contacts the second lateral side of the liner.