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    Structure and method to reduce shorting and process degradation in STT-MRAM devices
    52.
    发明授权
    Structure and method to reduce shorting and process degradation in STT-MRAM devices 有权

    公开(公告)号：US10243138B2

    公开(公告)日：2019-03-26

    申请号：US15906154

    申请日：2018-02-27

    Applicant: International Business Machines Corporation

    Inventor： Anthony J. Annunziata ,  Gen P. Lauer ,  Janusz J. Nowak ,  Eugene J. O'Sullivan

    IPC: H01L43/08 ,  H01L43/02 ,  H01L43/12

    Abstract: A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.

    STRUCTURE AND METHOD TO REDUCE SHORTING AND PROCESS DEGRADATION IN STT-MRAM DEVICES
    56.
    发明申请
    STRUCTURE AND METHOD TO REDUCE SHORTING AND PROCESS DEGRADATION IN STT-MRAM DEVICES 有权

    公开(公告)号：US20170229641A1

    公开(公告)日：2017-08-10

    申请号：US15499058

    申请日：2017-04-27

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Anthony J. Annunziata ,  Gen P. Lauer ,  Janusz J. Nowak ,  Eugene J. O'Sullivan

    IPC: H01L43/08 ,  H01L43/12

    CPC classification number: H01L43/08 ,  H01L43/02 ,  H01L43/12

    Abstract: A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.

    SPIN TORQUE MRAM FABRICATION USING NEGATIVE TONE LITHOGRAPHY AND ION BEAM ETCHING
    59.
    发明申请
    SPIN TORQUE MRAM FABRICATION USING NEGATIVE TONE LITHOGRAPHY AND ION BEAM ETCHING 有权
    旋转扭矩雕刻和离子束蚀刻的旋转扭矩MRAM制造

    公开(公告)号：US20170062708A1

    公开(公告)日：2017-03-02

    申请号：US14840176

    申请日：2015-08-31

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Anthony J. Annunziata ,  Armand A. Galan ,  Steve Holmes ,  Eric A. Joseph ,  Gen P. Lauer ,  Qinghuang Lin ,  Nathan P. Marchack

    IPC: H01L43/12

    CPC classification number: H01L43/12 ,  G03F7/70325 ,  G03F7/70425 ,  G11C11/161 ,  G11C2211/5615 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

    Abstract: A method for forming a memory device includes masking a photoresist material using a reticle and a developer having a polarity opposite that of the photoresist to provide an island of photoresist material. A planarizing layer is etched to establish a pillar of planarizing material defined by the island of photoresist material. A metal layer is etched to form a metal pillar having a diameter about the same as the pillar of planarizing material. A memory stack is etched to form a memory stack pillar having a diameter about the same as the metal pillar. A magnetoresistive memory cell includes a magnetic tunnel junction pillar having a circular cross section. The pillar has a pinned magnetic layer, a tunnel barrier layer, and a free magnetic layer. A first conductive contact is disposed above the magnetic tunnel junction pillar. A second conductive contact is disposed below the magnetic tunnel junction pillar.

    Abstract translation: 用于形成存储器件的方法包括使用掩模版和具有与光刻胶的极性相反的极性的显影剂掩蔽光致抗蚀剂材料以提供光致抗蚀剂材料岛。 蚀刻平坦化层以建立由光致抗蚀剂材料岛限定的平坦化材料的支柱。 蚀刻金属层以形成直径与平坦化材料的柱大致相同的金属柱。 蚀刻存储器堆叠以形成具有与金属柱大致相同直径的存储堆栈柱。 磁阻存储单元包括具有圆形横截面的磁隧道连接柱。 该柱具有钉扎磁性层，隧道势垒层和自由磁性层。 第一导电触点设置在磁隧道结柱的上方。 第二导电触点设置在磁隧道结柱的下方。

    III-V, SiGe, or Ge Base Lateral Bipolar Transistor and CMOS Hybrid Technology
    60.
    发明申请
    III-V, SiGe, or Ge Base Lateral Bipolar Transistor and CMOS Hybrid Technology 有权
    III-V，SiGe或Ge基侧向双极晶体管和CMOS混合技术

    公开(公告)号：US20170040219A1

    公开(公告)日：2017-02-09

    申请号：US15332207

    申请日：2016-10-24

    Applicant: International Business Machines Corporation

    Inventor： Josephine B. Chang ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

    IPC: H01L21/8249 ,  H01L29/66 ,  H01L21/24 ,  H01L27/06 ,  H01L21/84 ,  H01L29/735 ,  H01L29/10

    CPC classification number: H01L21/8249 ,  H01L21/244 ,  H01L21/84 ,  H01L27/0623 ,  H01L29/1008 ,  H01L29/456 ,  H01L29/6625 ,  H01L29/66545 ,  H01L29/735

    Abstract: In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. A dummy gate is formed on the wafer, wherein the dummy gate is present over a portion of the wafer that serves as a base of the bipolar transistor. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer surrounding the dummy gate. The dummy gate is removed selective to the dielectric filler layer, thereby exposing the base. The base is recessed. The base is re-grown from an epitaxial material selected from the group consisting of: SiGe, Ge, and a III-V material. Contacts are formed to the base. Techniques for co-fabricating a bipolar transistor and CMOS FET devices are also provided.

    Abstract translation: 一方面，在晶片上制造双极晶体管器件的方法包括以下步骤。 在晶片上形成虚拟栅极，其中伪栅极存在于作为双极晶体管的基极的晶片的一部分上。 晶圆被掺杂以在虚拟栅极的两侧上形成发射极和集电极区域。 介电填料层沉积在围绕虚拟栅极的晶片上。 对绝缘填料层选择性地去除伪栅极，从而露出基底。 基座凹进。 碱从由SiGe，Ge和III-V材料组成的组中选择的外延材料再生长。 触点形成在基座上。 还提供了用于共同制造双极晶体管和CMOS FET器件的技术。

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