公开(公告)号：US09812370B2

公开(公告)日：2017-11-07

申请号：US15332207

申请日：2016-10-24

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L21/336 ,  H01L21/8249 ,  H01L29/66 ,  H01L21/24 ,  H01L29/10 ,  H01L29/45 ,  H01L29/735 ,  H01L27/06 ,  H01L21/84

CPC classification number: H01L21/8249 ,  H01L21/244 ,  H01L21/84 ,  H01L27/0623 ,  H01L29/1008 ,  H01L29/456 ,  H01L29/6625 ,  H01L29/66545 ,  H01L29/735

Abstract: In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. A dummy gate is formed on the wafer, wherein the dummy gate is present over a portion of the wafer that serves as a base of the bipolar transistor. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer surrounding the dummy gate. The dummy gate is removed selective to the dielectric filler layer, thereby exposing the base. The base is recessed. The base is re-grown from an epitaxial material selected from the group consisting of: SiGe, Ge, and a III-V material. Contacts are formed to the base. Techniques for co-fabricating a bipolar transistor and CMOS FET devices are also provided.

公开(公告)号：US20170244024A1

公开(公告)日：2017-08-24

申请号：US15590545

申请日：2017-05-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony J. Annunziata ,  Armand A. Galan ,  Steve Holmes ,  Eric A. Joseph ,  Gen P. Lauer ,  Qinghuang Lin ,  Nathan P. Marchack

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/08

CPC classification number: H01L43/12 ,  G03F7/70325 ,  G03F7/70425 ,  G11C11/161 ,  G11C2211/5615 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A method of forming a pillar includes masking a photoresist material using a reticle and a developer having a polarity opposite that of the photoresist to provide an island of photoresist material. A layer under the island of photoresist material is etched to establish a pillar defined by the island of photoresist material.

公开(公告)号：US20170179194A1

公开(公告)日：2017-06-22

申请号：US14976339

申请日：2015-12-21

Applicant: International Business Machines Corporation ,  Tokyo Electron Limited

Inventor： Anthony J. Annunziata ,  Sebastian U. Engelmann ,  Eric A. Joseph ,  Gen P. Lauer ,  Nathan P. Marchack ,  Deborah A. Neumayer ,  Masahiro Yamazaki

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: A method of making a magnetic random access memory device comprises forming a magnetic tunnel junction on an electrode, the magnetic tunnel junction comprising a reference layer positioned in contact with the electrode, a tunnel barrier layer arranged on the reference layer, and a free layer arranged on the tunnel barrier layer; and depositing an encapsulating layer on and along sidewalls of the magnetic tunnel junction at a temperature of 40 to 60° C. using remote microwave plasma deposition wherein the encapsulation layer comprises silicon and nitrogen. An MRAM device made by the aforementioned method is also disclosed.

公开(公告)号：US09653679B1

公开(公告)日：2017-05-16

申请号：US15163253

申请日：2016-05-24

Applicant: International Business Machines Corporation

Inventor： Anthony J. Annunziata ,  Chandrasekharan Kothandaraman ,  Gen P. Lauer ,  Adam M. Pyzyna

IPC: H01L29/82 ,  H01L43/08 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L43/02 ,  H01L43/12

Abstract: A method of making a magnetoresistive structure is disclosed. The method includes forming a pillar structure including a magnetic tunnel junction on a substrate that includes a first electrode, depositing a stressed layer onto a pillar structure sidewall, and depositing a second electrode above the magnetic tunnel junction.

公开(公告)号：US20160233320A1

公开(公告)日：2016-08-11

申请号：US15134190

申请日：2016-04-20

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L29/66 ,  H01L21/321 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/02 ,  H01L21/3213

CPC classification number: H01L29/1037 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32115 ,  H01L21/32134 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/401 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.

公开(公告)号：US09391163B2

公开(公告)日：2016-07-12

申请号：US14505849

申请日：2014-10-03

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/06 ,  H01L21/02 ,  H01L21/321 ,  H01L21/3213

CPC classification number: H01L29/1037 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32115 ,  H01L21/32134 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/401 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.

Abstract translation: 制造场效应晶体管器件的方法包括：提供具有散热片堆叠的衬底，其具有：在衬底上的第一牺牲材料层，在第一牺牲材料层上的第一半导体材料层，以及在第一牺牲材料层上的第二牺牲材料层 半导体材料层。 该方法包括插入具有第二厚度的伪栅极，虚拟空隙和与第二面共面的外端。 该方法包括插入具有第一厚度和第一空隙的第一间隔件，并且具有与第一面共面的外端。 该方法包括蚀刻第二平面中的第一牺牲材料层和第四平面中的第二牺牲材料层。 该方法包括至少部分地去除第一间隔物。 该方法还包括插入具有第一厚度的第二间隔物。

公开(公告)号：US10170698B2

公开(公告)日：2019-01-01

申请号：US15590545

申请日：2017-05-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony J. Annunziata ,  Armand A. Galan ,  Steve Holmes ,  Eric A. Joseph ,  Gen P. Lauer ,  Qinghuang Lin ,  Nathan P. Marchack

IPC: G03F7/20 ,  H01L43/12 ,  H01L43/10 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L27/22

Abstract: A method of forming a pillar includes masking a photoresist material using a reticle and a developer having a polarity opposite that of the photoresist to provide an island of photoresist material. A layer under the island of photoresist material is etched to establish a pillar defined by the island of photoresist material.

公开(公告)号：US10170608B2

公开(公告)日：2019-01-01

申请号：US14754751

申请日：2015-06-30

Applicant: International Business Machines Corporation

Inventor： Szu-Lin Cheng ,  Michael A. Guillorn ,  Gen P. Lauer ,  Isaac Lauer

IPC: H01L29/06 ,  H01L29/775 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78

Abstract: A semiconductor device includes a first source/drain region a second source/drain region, and a gate region interposed between the first and second source/drain regions. At least one nanowire has a first end anchored to the first source/drain region and an opposing second end anchored to the second source/drain region such that the nanowire is suspended above the wafer in the gate region. At least one gate electrode is in the gate region. The gate electrode contacts an entire surface of the nanowire to define a gate-all-around configuration. At least one pair of oxidized spacers surrounds the at least one gate electrode to electrically isolate the at least one gate electrode from the first and second source/drain regions.

公开(公告)号：US20180309053A1

公开(公告)日：2018-10-25

申请号：US16023090

申请日：2018-06-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony J. Annunziata ,  Gen P. Lauer ,  Nathan P. Marchack

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16 ,  H01L27/22

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L27/222 ,  H01L27/224 ,  H01L43/02 ,  H01L43/08

Abstract: A magnetic memory device includes a magnetic memory stack including a bottom electrode and having a hard mask formed thereon. An encapsulation layer is formed over sides of the magnetic memory stack and has a thickness adjacent to the sides formed on the bottom electrode. A dielectric material is formed over the encapsulation layer and is removed from over the hard mask and gapped apart from the encapsulation layer on the sides of the magnetic memory stack to form trenches between the dielectric material and the encapsulation layer at the sides of the magnetic memory stack. A top electrode is formed over the hard mask and in the trenches such that the top electrode is spaced apart from the bottom electrode by at least the thickness.

公开(公告)号：US09853210B2

公开(公告)日：2017-12-26

申请号：US14943247

申请日：2015-11-17

Applicant: International Business Machines Corporation

Inventor： Anthony J. Annunziata ,  Gen P. Lauer ,  Nathan P. Marchack ,  Stephen M. Rossnagel

IPC: H01L43/12

CPC classification number: H01L43/12

Abstract: A method of making a magnetic random access memory (MRAM) device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer positioned in contact with the electrode, a free layer, and a tunnel barrier layer arranged between the reference layer and the free layer; and depositing an encapsulating layer on and along sidewalls of the MTJ by physical sputtering or ablation of a target material onto the MTJ.