DISTRIBUTED FILE TRANSFER WITH HIGH PERFORMANCE

    公开(公告)号:US20180227355A1

    公开(公告)日:2018-08-09

    申请号:US15428203

    申请日:2017-02-09

    Abstract: A method for distributed file transfers with high performance and reliability includes creating, on a first Trivial File Transfer Protocol (TFTP) server, a global cache, where the global cache is used to store up to a first portion of a data file. The method further includes storing, on the first TFTP server, in the global cache, one or more continuous data blocks that have exceeded a defined first request rate threshold, where the one or more continuous data blocks make up a subset of the data blocks of the first portion of the data file. The method further includes predicting, on the first TFTP server, a next data block in the data file to be stored in the global cache and in response to predicting the next data block, storing, on the first TFTP server, the next data block in the global cache.

    Adaptive reference tuning for endurance enhancement of non-volatile memories

    公开(公告)号:US09250816B2

    公开(公告)日:2016-02-02

    申请号:US14013485

    申请日:2013-08-29

    Abstract: A wear leveling technique is employed in a memory device so that the cycling history of a memory block is represented by the cycling history of a representative memory cell or a small number of representative memory cells. A control logic block tracks the cycling history of the one or more representative memory cells. A table tabulating the predicted shift in an optimal value for a reference variable for a sensing circuit as a function of cycling history is provided within the memory device. Prior to sensing a memory cell, the control logic block checks the total number of cycling in the one or more representative memory cells and adjusts the value for the reference variable in the sensing circuit, thereby providing an optimal value for the reference variable in the sensing circuit for each sensing cycle of the memory device.

    DETECTING DEVIATIONS BETWEEN EVENT LOG AND PROCESS MODEL

    公开(公告)号:US20150302314A1

    公开(公告)日:2015-10-22

    申请号:US14748867

    申请日:2015-06-24

    Abstract: A method for detecting deviations between an event log and a process model includes converting the process model into a probability process model, the probability process model comprising multiple nodes in multiple hierarchies and probability distribution associated with the multiple nodes, a leaf node among the multiple nodes corresponding to an activity in the process model; detecting differences between at least one event sequence contained in the event log and the probability process model according to a correspondence relationship; and identifying the differences as the deviations in response to the differences exceeding a predefined threshold; wherein the correspondence relationship describes a correspondence relationship between an event in one event sequence of the at least one event sequence and a leaf node in the probability process model.

    Self-aligned patterning technique for semiconductor device features
    56.
    发明授权
    Self-aligned patterning technique for semiconductor device features 有权
    半自动对准图案化技术

    公开(公告)号:US08927424B1

    公开(公告)日:2015-01-06

    申请号:US13931798

    申请日:2013-06-28

    Abstract: A method for fabricating a semiconductor device utilizing a plurality of masks and spacers. The method includes forming parallel first trenches in a substrate using a first lithographic process. The substrate includes sidewalls adjacent to the parallel first trenches. Forming first spacers adjacent to the sidewalls. Removing the sidewalls, which in part includes using a second lithographic process. Forming second spacers adjacent to the first spacers, resulting in spacer ridges. Etching portions of the substrate between the spacer ridges resulting in second trenches.

    Abstract translation: 一种利用多个掩模和间隔物制造半导体器件的方法。 该方法包括使用第一光刻工艺在衬底中形成平行的第一沟槽。 衬底包括与平行的第一沟槽相邻的侧壁。 形成与侧壁相邻的第一间隔物。 去除侧壁,其部分地包括使用第二光刻工艺。 与第一间隔物相邻形成第二间隔物,产生间隔脊。 在间隔脊之间蚀刻基板的部分,产生第二沟槽。

    Single-mask spacer technique for semiconductor device features
    57.
    发明授权
    Single-mask spacer technique for semiconductor device features 有权
    用于半导体器件特征的单掩模间隔技术

    公开(公告)号:US08652901B1

    公开(公告)日:2014-02-18

    申请号:US13783388

    申请日:2013-03-03

    Abstract: A method for fabricating vertical surround gate structures in semiconductor device arrays. The method includes forming pillars separated by vertical and horizontal trenches on a substrate. Forming a gate layer over the pillars and trenches such that the gate layer forms gate trenches in the horizontal trenches. The method includes forming fillers within the gate trenches, and planarizing the gate layer and fillers. The method also includes successively etching a first portion of the gate layer, removing the fillers, and etching a second portion of the gate layer.

    Abstract translation: 一种在半导体器件阵列中制造垂直环绕栅极结构的方法。 该方法包括在衬底上形成由垂直和水平沟槽分隔的柱。 在柱和沟槽上形成栅极层,使得栅极层在水平沟槽中形成栅极沟槽。 该方法包括在栅极沟槽内形成填料,并平整栅极层和填料。 该方法还包括连续地蚀刻栅极层的第一部分,去除填料并蚀刻栅极层的第二部分。

    Edge computing workload balancing
    58.
    发明授权

    公开(公告)号:US11586480B2

    公开(公告)日:2023-02-21

    申请号:US17102581

    申请日:2020-11-24

    Abstract: A set of workload criteria is determined from a workload associated with a plurality of sources. The workload is divided among a set of workload groups according to the set of workload criteria and a first workload scheduler. A set of edge computing resources is assigned to each workload group within the set according to the set of workload criteria and the set of workload groups. A portion of the workload associated with a subset of the plurality of sources is handled by a first subset of edge computing resources and a second workload scheduler, where the subset of sources is associated with a first workload group. The handling includes balancing, by the second workload scheduler, the portion of the workload among the subset of sources. The handled workload is reported to a control center.

    Detecting deviations between event log and process model

    公开(公告)号:US11514348B2

    公开(公告)日:2022-11-29

    申请号:US16563070

    申请日:2019-09-06

    Abstract: A method for detecting deviations between an event log and a process model includes converting the process model into a probability process model, the probability process model comprising multiple nodes in multiple hierarchies and probability distribution associated with the multiple nodes, a leaf node among the multiple nodes corresponding to an activity in the process model; detecting differences between at least one event sequence contained in the event log and the probability process model according to a correspondence relationship; and identifying the differences as the deviations in response to the differences exceeding a predefined threshold; wherein the correspondence relationship describes a correspondence relationship between an event in one event sequence of the at least one event sequence and a leaf node in the probability process model.

Patent Agency Ranking