公开(公告)号：US10347617B2

公开(公告)日：2019-07-09

申请号：US15695198

申请日：2017-09-05

申请人： International Business Machines Corporation ,  STMicroelectronics, Inc.

发明人： Lawrence A. Clevenger ,  Carl J. Radens ,  Yiheng Xu ,  John H. Zhang

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L23/02 ,  H01L25/18 ,  H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L23/13 ,  H01L23/15

摘要： Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the first stair, wherein the at least one additional chip is vertically spaced apart from the first chip.

公开(公告)号：US10325778B2

公开(公告)日：2019-06-18

申请号：US15801039

申请日：2017-11-01

申请人： International Business Machines Corporation

发明人： Lawrence A. Clevenger ,  John H. Zhang ,  Carl Radens

IPC分类号： H01L21/302 ,  H01L21/308 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768

摘要： A chemical material is deposited on a surface of a substrate. A mandrel composition is deposited on a surface of the chemical material. A mandrel hard mask pattern is deposited on a surface of the mandrel composition. The mandrel composition is etched. The mandrel hard mask pattern is removed. A plurality of spacer materials are deposited sequentially onto a surface of the chemical material and a surface of the mandrel composition. A portion of each of the plurality of spacer materials are removed sequentially. A remainder of the mandrel composition is removed. The substrate is etched. The chemical material and at least one of the spacer materials of the plurality of spacer materials are removed.

公开(公告)号：US20190067023A1

公开(公告)日：2019-02-28

申请号：US15690540

申请日：2017-08-30

申请人： International Business Machines Corporation

发明人： Lawrence A. Clevenger ,  John H. Zhang ,  Carl Radens

IPC分类号： H01L21/308

摘要： A chemical material is deposited on a surface of a substrate. A mandrel composition is deposited on a surface of the chemical material. A mandrel hard mask pattern is deposited on a surface of the mandrel composition. The mandrel composition is etched. The mandrel hard mask pattern is removed. A plurality of spacer materials are deposited sequentially onto a surface of the chemical material and a surface of the mandrel composition. A portion of each of the plurality of spacer materials are removed sequentially. A remainder of the mandrel composition is removed. The substrate is etched. The chemical material and at least one of the spacer materials of the plurality of spacer materials are removed.

公开(公告)号：US20180286750A1

公开(公告)日：2018-10-04

申请号：US15815173

申请日：2017-11-16

申请人： International Business Machines Corporation

发明人： Lawrence A. Clevenger ,  Carl J. Radens ,  John H. Zhang

IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L21/8234 ,  H01L21/311

CPC分类号： H01L21/76897 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76877 ,  H01L21/823475 ,  H01L21/823487 ,  H01L23/5226 ,  H01L23/528

摘要： A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.

公开(公告)号：US09882028B2

公开(公告)日：2018-01-30

申请号：US15196386

申请日：2016-06-29

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Balasubramanian S. Pranatharthiharan ,  John H. Zhang

IPC分类号： H01L21/311 ,  H01L29/66 ,  H01L21/3115 ,  H01L21/02 ,  H01L21/033

CPC分类号： H01L29/66795 ,  H01L21/02129 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31105 ,  H01L21/3115 ,  H01L29/66545

摘要： A method for forming fins of a semiconductor device comprises forming a first hardmask on a substrate, a sacrificial layer on the first hardmask, and a second hardmask on the sacrificial layer. Portions of the second hardmask and the sacrificial layer are removed to form a mandrel. Spacers are formed adjacent to the sacrificial mandrel. A second sacrificial layer is deposited and portions of the second sacrificial layer are removed to expose portions of the spacers and the first hardmask. A first doped region and a second doped region are formed by annealing. The second hardmask and the sacrificial spacer are removed. Undoped portions of the sacrificial mandrel and the second sacrificial layer are removed to further expose portions of the first hardmask. Exposed portions of the first hardmask are removed to expose portions of the semiconductor substrate, and exposed portions of the semiconductor substrate are removed to form fins.

公开(公告)号：US20180006138A1

公开(公告)日：2018-01-04

申请号：US15196386

申请日：2016-06-29

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Balasubramanian S. Pranatharthiharan ,  John H. Zhang

IPC分类号： H01L29/66 ,  H01L21/311 ,  H01L21/033 ,  H01L21/3115 ,  H01L21/02

CPC分类号： H01L29/66795 ,  H01L21/02129 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31105 ,  H01L21/3115 ,  H01L29/66545

摘要： A method for forming fins of a semiconductor device comprises forming a first hardmask on a substrate, a sacrificial layer on the first hardmask, and a second hardmask on the sacrificial layer. Portions of the second hardmask and the sacrificial layer are removed to form a mandrel. Spacers are formed adjacent to the sacrificial mandrel. A second sacrificial layer is deposited and portions of the second sacrificial layer are removed to expose portions of the spacers and the first hardmask. A first doped region and a second doped region are formed by annealing. The second hardmask and the sacrificial spacer are removed. Undoped portions of the sacrificial mandrel and the second sacrificial layer are removed to further expose portions of the first hardmask. Exposed portions of the first hardmask are removed to expose portions of the semiconductor substrate, and exposed portions of the semiconductor substrate are removed to form fins.

公开(公告)号：US09837394B2

公开(公告)日：2017-12-05

申请号：US14956834

申请日：2015-12-02

申请人： International Business Machines Corporation ,  STMicroelectronics, Inc.

发明人： Lawrence A. Clevenger ,  Carl J. Radens ,  Yiheng Xu ,  John H. Zhang

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/18 ,  H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48

CPC分类号： H01L25/18 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15156 ,  H01L2924/15313 ,  H01L2924/157

摘要： Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the first stair, wherein the at least one additional chip is vertically spaced apart from the first chip.

公开(公告)号：US09741609B1

公开(公告)日：2017-08-22

申请号：US15340226

申请日：2016-11-01

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Balasubramanian S. Pranatharthi Haran ,  John H. Zhang

IPC分类号： H01L21/335 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535

CPC分类号： H01L21/76847 ,  H01L21/76805 ,  H01L21/76865 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53209

摘要： A method of fabricating features of a semiconductor device includes forming a contact over a substrate, the contact including a cobalt core and a liner layer arranged on sidewalls, wherein the contact includes a portion that is laterally surrounded by an interlevel dielectric (ILD); depositing another layer of ILD on the contact; etching a first opening in the ILD to expose a surface of the contact; removing the liner layer of the contact to expose a portion of the cobalt core; etching the ILD that laterally surrounds the contact to form a second opening beneath the first opening, the second opening having a width that is less than the first opening; depositing a liner on sidewalls of the first opening, the second opening, and directly on the cobalt core; and depositing a metal on the liner layer to form an interconnect structure.

公开(公告)号：US20160293589A1

公开(公告)日：2016-10-06

申请号：US15175738

申请日：2016-06-07

申请人： International Business Machines Corporation ,  STMicroelectronics, Inc.

发明人： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Edem Wornyo

IPC分类号： H01L27/01 ,  H01L23/525

CPC分类号： H01L27/016 ,  H01L21/31053 ,  H01L21/3212 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/5252 ,  H01L23/5256 ,  H01L28/20 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers. The resistors and capacitors thus formed as a set of integrated circuit elements are suitable for use as microelectronic fuses and antifuses, respectively, to protect underlying microelectronic circuits.

摘要翻译： 半导体处理步骤的顺序允许在公共结构内形成垂直和水平的纳米级蛇形电阻器和平行板电容器。 该方法利用CMP工艺不均匀性，其中绝缘材料的CMP抛光速率根据某些底层的形貌而变化。 通过在绝缘材料层之下建立这样的形貌，可以通过利用差分抛光速率在不同的区域产生绝缘体的不同膜厚度，从而避免使用光刻掩模。 在一个实施例中，使用仅需要两个掩模层的工艺，可以在公共介电块内形成多个电阻器和电容器作为紧凑的集成结构。 这样形成为一组集成电路元件的电阻器和电容器分别适合用作微电子熔丝和反熔丝，以保护下面的微电子电路。

公开(公告)号：US20160247722A1

公开(公告)日：2016-08-25

申请号：US15143969

申请日：2016-05-02

申请人： International Business Machines Corporation ,  STMICROELECTRONICS, INC.

发明人： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Richard Stephen Wise ,  Akil K. Sutton ,  Terry Allen Spooner ,  Nicole A. Saulnier

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/311 ,  H01L23/522

CPC分类号： H01L21/76897 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. The enlarged diameter vias make direct contact with at least three sides of the underlying metal lines, and can be aligned asymmetrically with respect to the metal line to increase the packing density of the metal pattern. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. An interconnect structure having enlarged diameter vias can also feature air gaps to reduce the chance of dielectric breakdown. By allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.