公开(公告)号：US20140231877A1

公开(公告)日：2014-08-21

申请号：US13769500

申请日：2013-02-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： James W. Adkisson ,  David L. Harame ,  Qizhi Liu

IPC: H01L29/66 ,  H01L29/737

CPC classification number: H01L29/7371 ,  H01L29/0649 ,  H01L29/267 ,  H01L29/66242 ,  H01L29/7327 ,  H01L29/737 ,  H01L29/7378

Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate. An intrinsic base is formed on the emitter. A collector is formed that is separated from the emitter by the intrinsic base. The collector includes a semiconductor material having an electronic bandgap greater than an electronic bandgap of a semiconductor material of the device region.

Abstract translation: 双极结晶体管的制造方法，器件结构和设计结构。 在衬底中限定的器件区域中形成发射极。 在发射极上形成一个本征基极。 形成了通过内在基极与发射极分离的集电极。 集电体包括具有大于器件区域的半导体材料的电子带隙的电子带隙的半导体材料。

公开(公告)号：US08673726B2

公开(公告)日：2014-03-18

申请号：US13762445

申请日：2013-02-08

Applicant: International Business Machines Corporation

Inventor： David L. Harame ,  Russell T. Herrin ,  Qizhi Liu

IPC: H01L21/00

CPC classification number: H01L29/0649 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/7378

Abstract: Disclosed are embodiments of a bipolar or heterojunction bipolar transistor and a method of forming the transistor. The transistor can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method allows for self-aligning of the emitter to base regions and incorporates the use of a sacrificial dielectric layer, which must be thick enough to withstand etch and cleaning processes and still remain intact to function as an etch stop layer when the conductive strap is subsequently formed. A chemically enhanced high pressure, low temperature oxidation (HIPOX) process can be used to form such a sacrificial dielectric layer.

Abstract translation: 公开了双极或异质结双极晶体管的实施例以及形成晶体管的方法。 晶体管可以包含夹在本征基极层和凸起的非本征基极层之间的电介质层，以将集电极 - 基极电容Ccb，用于本征基极层的侧壁限定的导电带限制到外部基极层连接区域以降低基极电阻 Rb和外部基极层和发射极层之间的介电间隔物，以减少基极 - 发射极的Cbe电容。 该方法允许发射极与基极区域的自对准，并结合使用牺牲介电层，其必须足够厚以承受蚀刻和清洁过程，并且当导电带是 随后形成。 可以使用化学增强的高压，低温氧化（HIPOX）工艺来形成这种牺牲介电层。

公开(公告)号：US20130149832A1

公开(公告)日：2013-06-13

申请号：US13762445

申请日：2013-02-08

Applicant: International Business Machines Corporation

Inventor： David L. Harame ,  Russell T. Herrin ,  Qizhi Liu

IPC: H01L29/06

CPC classification number: H01L29/0649 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/7378

Abstract: Disclosed are embodiments of a bipolar or heterojunction bipolar transistor and a method of forming the transistor. The transistor can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method allows for self-aligning of the emitter to base regions and incorporates the use of a sacrificial dielectric layer, which must be thick enough to withstand etch and cleaning processes and still remain intact to function as an etch stop layer when the conductive strap is subsequently formed. A chemically enhanced high pressure, low temperature oxidation (HIPOX) process can be used to form such a sacrificial dielectric layer.

Abstract translation: 公开了双极或异质结双极晶体管的实施例以及形成晶体管的方法。 晶体管可以包含夹在本征基极层和凸起的非本征基极层之间的电介质层，以将集电极 - 基极电容Ccb，用于本征基极层的侧壁限定导电带限制到外部基极层连接区域以降低基极电阻 Rb和外部基极层和发射极层之间的介电间隔物，以减少基极 - 发射极的Cbe电容。 该方法允许发射极与基极区域的自对准，并结合使用牺牲介电层，其必须足够厚以承受蚀刻和清洁过程，并且当导电带是 随后形成。 可以使用化学增强的高压，低温氧化（HIPOX）工艺来形成这种牺牲介电层。

公开(公告)号：US20130130462A1

公开(公告)日：2013-05-23

申请号：US13740673

申请日：2013-01-14

Applicant: International Business Machines Corporation

Inventor： David L. Harame ,  Alvin J. Joseph ,  Qizhi Liu ,  Ramana M. Malladi

IPC: H01L29/73

CPC classification number: H01L29/73 ,  H01L29/0821 ,  H01L29/66272 ,  H01L29/732

Abstract: Embodiments of the present invention include a method for forming a tunable semiconductor device. In one embodiment, the method comprises: forming a semiconductor substrate; patterning a first mask over the semiconductor substrate; doping regions of the semiconductor substrate not protected by the first mask to form a first discontinuous subcollector; removing the first mask; patterning a second mask over the semiconductor substrate; doping regions of the semiconductor substrate not protected by the second mask and on top of the first discontinuous subcollector to form a second discontinuous subcollector; removing the second mask; and forming a single continuous collector above the second discontinuous subcollector.

Abstract translation: 本发明的实施例包括形成可调谐半导体器件的方法。 在一个实施例中，该方法包括：形成半导体衬底; 在半导体衬底上图案化第一掩模; 不受第一掩模保护的半导体衬底的掺杂区域以形成第一不连续子集电极; 去除第一个面罩; 在半导体衬底上图案化第二掩模; 所述半导体衬底的掺杂区域不被所述第二掩模保护并且在所述第一不连续子集电极的顶部上以形成第二不连续子集电极; 去除第二个掩模; 以及在第二不连续子集电极上方形成单个连续集电器。

公开(公告)号：US11152467B2

公开(公告)日：2021-10-19

申请号：US16516803

申请日：2019-07-19

Applicant: International Business Machines Corporation

Inventor： Renata Camillo-Castillo ,  David L. Harame ,  Qizhi Liu

IPC: H01L29/10 ,  H01L21/225 ,  H01L21/324 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/737 ,  H01L29/732

Abstract: A device structure for a bipolar junction transistor includes a base layer made of a semiconductor material. An emitter is disposed on a first portion of the base layer. A dopant-containing layer is disposed on a second portion of the base layer. A hardmask is disposed on the base layer. The hardmask includes a window aligned with the second portion of the base layer. Deposits of the dopant-containing layer are limited to exposed surfaces of: the first portion that is disposed on a top surface of the base layer inside of the window.

公开(公告)号：US10804364B2

公开(公告)日：2020-10-13

申请号：US16031371

申请日：2018-07-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Vibhor Jain ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/812 ,  H01L29/49 ,  H01L29/47 ,  H01L27/12 ,  H01L29/51

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

公开(公告)号：US10680074B2

公开(公告)日：2020-06-09

申请号：US15944018

申请日：2018-04-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Vibhor Jain ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L21/28 ,  H01L27/12 ,  H01L29/47 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/812

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

公开(公告)号：US09356014B2

公开(公告)日：2016-05-31

申请号：US14522652

申请日：2014-10-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： William F. Clark, Jr. ,  Qizhi Liu ,  John J. Pekarik ,  Yun Shi ,  Yanli Zhang

IPC: H01L27/06 ,  H01L21/8249 ,  H01L21/8234 ,  H01L29/04 ,  H01L27/092 ,  H01L29/161 ,  H01L29/45 ,  H01L29/735 ,  H01L29/40 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/73

CPC classification number: H01L27/0623 ,  H01L21/823418 ,  H01L21/8249 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/04 ,  H01L29/161 ,  H01L29/402 ,  H01L29/45 ,  H01L29/66659 ,  H01L29/7302 ,  H01L29/735 ,  H01L29/78 ,  H01L29/7817 ,  H01L29/7835

Abstract: Semiconductor structures and methods of manufacture are disclosed herein. Specifically, disclosed herein are methods of manufacturing a high-voltage metal-oxide-semiconductor field-effect transistor and respective structures. A method includes forming a field-effect transistor (FET) on a substrate in a FET region, forming a high-voltage FET (HVFET) on a dielectric stack over a over lightly-doped diffusion (LDD) drain in a HVFET region, and forming an NPN on the substrate in an NPN region.

Abstract translation: 本文公开了半导体结构和制造方法。 具体地，本文公开了制造高压金属氧化物半导体场效应晶体管和各种结构的方法。 一种方法包括在FET区域的衬底上形成场效应晶体管（FET），在HVFET区域中的过掺杂掺杂扩散（LDD）漏极上的介质堆叠上形成高电压FET（HVFET），以及 在NPN区域的基板上形成NPN。

公开(公告)号：US20160049492A1

公开(公告)日：2016-02-18

申请号：US14457524

申请日：2014-08-12

Applicant: International Business Machines Corporation

Inventor： Joseph R. Greco ,  Qizhi Liu ,  Aaron L. Vallett ,  Robert F. Vatter

IPC: H01L29/66 ,  H01L29/10 ,  H01L21/768 ,  H01L29/732

CPC classification number: H01L29/732 ,  H01L21/76232 ,  H01L21/76879 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0826 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/16 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/456 ,  H01L29/66234 ,  H01L29/66272 ,  H01L29/66287

Abstract: Various particular embodiments include a method of amorphizing a portion of silicon underneath the N+ base section of a PNP transistor structure. After amorphizing, the method can include selectively etching that implant-amorphized silicon to trim the collector-base area and collector-base junction. The selective etching is enhanced because the unimplanted silicon region etches at a distinct rate than the implant-amorphized silicon, allowing for control over the trimming of the collector-base junction.

Abstract translation: 各种具体实施例包括使PNP晶体管结构的N +基极部分下方的硅的一部分非晶化的方法。 在非晶化之后，该方法可以包括选择性地蚀刻该植入物非晶化硅以修整集电极 - 基极区域和集电极 - 基极结。 选择性蚀刻被增强，因为未植入的硅区域以与植入物非晶化硅不同的速率蚀刻，允许控制集电极 - 基极结的修整。

公开(公告)号：US09240448B2

公开(公告)日：2016-01-19

申请号：US14734713

申请日：2015-06-09

Applicant: International Business Machines Corporation

Inventor： James W. Adkisson ,  James R. Elliott ,  David L. Harame ,  Marwan H. Khater ,  Robert K. Leidy ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/732 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/0649 ,  H01L29/045 ,  H01L29/0804 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66257 ,  H01L29/66287 ,  H01L29/73 ,  H01L29/7325 ,  H01L29/7375

Abstract: Device structures for a bipolar junction transistor. The device structure includes a collector region, an intrinsic base formed on the collector region, an emitter coupled with the intrinsic base and separated from the collector by the intrinsic base, and an isolation region extending through the intrinsic base to the collector region. The isolation region is formed with a first section having first sidewalls that extend through the intrinsic base and a second section with second sidewalls that extend into the collector region. The second sidewalls are inclined relative to the first sidewalls. The isolation region is positioned in a trench that is formed with first and second etching process in which the latter etches different crystallographic directions of a single-crystal semiconductor material at different etch rates.

Abstract translation: 双极结型晶体管的器件结构。 器件结构包括集电极区域，形成在集电极区域上的本征基极，与本征基极耦合并与集电极与本征基极分离的发射极，以及延伸穿过本征基极到集电极区域的隔离区域。 隔离区形成有具有延伸穿过本征基底的第一侧壁的第一部分和具有延伸到收集器区域中的第二侧壁的第二部分。 第二侧壁相对于第一侧壁倾斜。 隔离区域位于形成有第一和第二蚀刻工艺的沟槽中，其中后者以不同的蚀刻速率蚀刻单晶半导体材料的不同晶体方向。