公开(公告)号：US20190251430A1

公开(公告)日：2019-08-15

申请号：US15895162

申请日：2018-02-13

Applicant: International Business Machines Corporation

Inventor： Tayfun Gokmen ,  Seyoung Kim ,  Jinwook Oh

IPC: G06N3/08 ,  G06N3/04

CPC classification number: G06N3/08 ,  G06N3/04

Abstract: A resistive processing unit (RPU) includes a coincidence detector to detect an overlapping signal between a row update line and a column update line, a counter receiving an output of the logic gate, storing a weight as a training methodology of the RPU, and changing the stored weight in response to an up/down signal applied to the counter, a digital to analog converter (DAC) receiving a digital value output from the counter and converting the digital value into an analog voltage, and a weight reading circuit for reading the weight using the analog voltage.

公开(公告)号：US10373051B2

公开(公告)日：2019-08-06

申请号：US14966394

申请日：2015-12-11

Applicant: International Business Machines Corporation

Inventor： Tayfun Gokmen ,  Seyoung Kim ,  Yurii A. Vlasov

IPC: G06N3/04 ,  G06N3/08 ,  G06N3/063

Abstract: Embodiments are directed to a two-terminal resistive processing unit (RPU) having a first terminal, a second terminal and an active region. The active region effects a non-linear change in a conduction state of the active region based on at least one first encoded signal applied to the first terminal and at least one second encoded signal applied to the second terminal. The active region is configured to locally perform a data storage operation of a training methodology based at least in part on the non-linear change in the conduction state. The active region is further configured to locally perform a data processing operation of the training methodology based at least in part on the non-linear change in the conduction state.

公开(公告)号：US10360283B2

公开(公告)日：2019-07-23

申请号：US15838992

申请日：2017-12-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tayfun Gokmen ,  Oguzhan Murat Onen

IPC: G06G7/16 ,  G06N3/08 ,  G06F17/16 ,  G06F7/523 ,  G06F7/535 ,  G06F7/544 ,  G06N3/063

Abstract: A method, computer program product, and circuit are provided for noise and bound management for a Resistive Processing Unit (RPU) array having an op-amp. The method includes reducing the noise in an output signal from the RPU array by using a largest value, in a sigma vector having a plurality of values, as a representation for a window for an input signal to the RPU array. The input signal to the RPU array is formed from the plurality of values. The method further includes sensing saturation at an output of the op-amp. The method also includes managing the bound to eliminate the saturation by reducing the plurality of values from which the input signal to the RPU is formed.

公开(公告)号：US20180300627A1

公开(公告)日：2018-10-18

申请号：US15842724

申请日：2017-12-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tayfun Gokmen ,  Oguzhan Murat Önen

IPC: G06N3/08 ,  G06F5/01 ,  G06F17/16

Abstract: A computer-implemented method and computer processing system are provided for update management for a neural network. The method includes performing an isotropic update process on the neural network using a Resistive Processing Unit. The isotropic update process uses a multiplicand and a multiplier from a multiplication operation. The performing step includes scaling the multiplicand and the multiplier to have a same order of magnitude.

公开(公告)号：US20180075350A1

公开(公告)日：2018-03-15

申请号：US15609691

申请日：2017-05-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tayfun Gokmen

IPC: G06N3/08

CPC classification number: G06N3/08 ,  G06N3/063 ,  G06N3/084

Abstract: Technical solutions are described for improving efficiency of training a resistive processing unit (RPU) array using a neural network training methodology. An example method includes reducing asymmetric RPUs from the RPU array by determining an asymmetric value of an RPU from the RPU array, and burning the RPU in response to the asymmetry value being above a predetermined threshold. The RPU can be burned by causing an electric voltage across the RPU to be above a predetermined limit. The method further includes initiating the training methodology for the RPU array after the asymmetric RPUs from the RPU array are reduced.

公开(公告)号：US20180060726A1

公开(公告)日：2018-03-01

申请号：US15251278

申请日：2016-08-30

Applicant: International Business Machines Corporation

Inventor： Tayfun Gokmen ,  Yurii A. Vlasov

IPC: G06N3/08 ,  G06N3/063

CPC classification number: G06N3/0635 ,  G06N3/084

Abstract: A device, system, product and method of controlling resistive processing units (RPUs), includes applying an input voltage signal to each node of an array of resistive processing units, and controlling a learning rate of the array of resistive processing units by varying an amplitude of the input voltage signal to the array of resistive processing units. A conductance state of the array of resistive processing units is varied according to the amplitude received at each of the resistive processing units of the array of resistive processing units. The controlling of the amplitude of input voltage signal is according to a processor of a control device.

公开(公告)号：US20180005115A1

公开(公告)日：2018-01-04

申请号：US15196350

申请日：2016-06-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tayfun Gokmen ,  Yurii A. Vlasov

IPC: G06N3/08 ,  G06N3/04

CPC classification number: G06N3/084 ,  G06N3/0635

Abstract: A neural network system comprises a plurality of neurons, comprising a layer of input neurons, one or more layers of hidden neurons, and a layer of output neurons. The system further comprises a plurality of arrays of weights, each array of weights being configured to receive a plurality of discrete data points from a first layer of neurons and to produce a corresponding discrete data point to a second layer of neurons during a feed forward operation, each array of weights comprising a plurality of resistive processing units (RPU) having respective settable resistances. The system includes a neuron control system configured to control an operation mode of each of the plurality of neurons, wherein the operation mode comprises: a feed forward mode, a back propagation mode, and a weight update mode.

公开(公告)号：US09608160B1

公开(公告)日：2017-03-28

申请号：US15016799

申请日：2016-02-05

Applicant: International Business Machines Corporation

Inventor： Can Bayram ,  Cheng-Wei Cheng ,  Tayfun Gokmen ,  Ning Li ,  John A. Ott ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC: H01L29/15 ,  H01L33/00 ,  H01L33/12 ,  H01L33/32 ,  H01L33/22 ,  H01L33/18 ,  H01L33/36

CPC classification number: H01L33/007 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L33/12 ,  H01L33/16 ,  H01L33/18 ,  H01L33/22 ,  H01L33/32 ,  H01L33/36 ,  H01L2933/0016 ,  H01S5/021 ,  H01S5/3201 ,  H01S5/3202 ,  H01S5/34333

Abstract: After forming patterned dielectric material structures over a (100) silicon substrate, portions of the silicon substrate that are not covered by the patterned dielectric material structures are removed to provide a plurality of openings within the silicon substrate. Each opening exposes a surface of the silicon substrate having a (111) crystalline plane. A buffer layer is then formed on the exposed surfaces of the patterned dielectric material structures and the silicon substrate. A dual phase Group III nitride structure including a cubic phase region is formed filling a space between each neighboring pair of the patterned dielectric material structures and one of the openings located beneath the space. Finally, at least one Group III nitride layer is epitaxially deposited over the cubic phase region of the dual phase Group III nitride structure.

公开(公告)号：US12293281B2

公开(公告)日：2025-05-06

申请号：US17226416

申请日：2021-04-09

Applicant: International Business Machines Corporation

Inventor： Tayfun Gokmen

IPC: G06N3/065 ,  G06F11/14 ,  G06F17/16 ,  G06N3/08 ,  G11C5/06

Abstract: Embodiments disclosed herein include a method of training a DNN. A processor initializes an element of an A matrix. The element may include a resistive processing unit. A processor determines incremental weight updates by updating the element with activation values and error values from a weight matrix multiplied by a chopper value. A processor reads an update voltage from the element. A processor determines a chopper product by multiplying the update voltage by the chopper value. A processor directs storage of an element of a hidden matrix. The element of the hidden matrix may include a summation of continuous iterations of the chopper product. A processor updates a corresponding element of a weight matrix based on the element of the hidden matrix reaching a threshold state.

公开(公告)号：US12112264B2

公开(公告)日：2024-10-08

申请号：US17121930

申请日：2020-12-15

Applicant: International Business Machines Corporation

Inventor： Malte Johannes Rasch ,  Tayfun Gokmen ,  Seyoung Kim

IPC: G06N3/08 ,  G06N3/063

CPC classification number: G06N3/08 ,  G06N3/063

Abstract: A device which comprises an array of resistive processing unit (RPU) cells, first control lines extending in a first direction across the array of RPU cells, and second control lines extending in a second direction across the array of RPU cells. Peripheral circuitry comprising readout circuitry is coupled to the first and second control lines. A control system generates control signals to control the peripheral circuitry to perform a first operation and a second operation on the array of RPU cells. The control signals include a first configuration control signal to configure the readout circuitry to have a first hardware configuration when the first operation is performed on the array of RPU cells, and a second configuration control signal to configure the readout circuitry to have a second hardware configuration, which is different from the first hardware configuration, when the second operation is performed on the array of RPU cells.