公开(公告)号：US20200070150A1

公开(公告)日：2020-03-05

申请号：US16419684

申请日：2019-05-22

Applicant: International Business Machines Corporation

Inventor： Chi-Chun Liu ,  Yann Mignot ,  Joshua T. Smith ,  Bassem M. Hamieh ,  Nelson Felix ,  Robert L. Bruce

IPC: B01L3/00 ,  B81C1/00 ,  B81B7/00

Abstract: A microfluidic chip with high volumetric flow rate is provided that includes at least two vertically stacked microfluidic channel layers, each microfluidic channel layer including an array of spaced apart pillars. Each microfluidic channel layer is interconnected by an inlet/outlet opening that extends through the microfluidic chip. The microfluidic chip is created without wafer to wafer bonding thus circumventing the cost and yield issues associated with microfluidic chips that are created by wafer bonding.

公开(公告)号：US20200066526A1

公开(公告)日：2020-02-27

申请号：US16669861

申请日：2019-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hsueh-Chung Chen ,  Yongan Xu ,  Lawrence A. Clevenger ,  Yann Mignot ,  Cornelius Brown Peethala

IPC: H01L21/033 ,  G03F7/00 ,  H01L21/027 ,  G03F7/20 ,  G03F7/09 ,  H01L21/02 ,  H01L21/3105 ,  G03F7/16

Abstract: A semiconductor device includes at least one mandrel including a dielectric material, and at least one non-mandrel including a hard mask material having an etch property substantially similar to that of the dielectric material.

公开(公告)号：US20190237562A1

公开(公告)日：2019-08-01

申请号：US15886539

申请日：2018-02-01

Applicant: international Business Machines Corporation

Inventor： Chi-Chun Liu ,  Chun Wing Yeung ,  Robin Hsin Kuo Chao ,  Zhenxing Bi ,  Kristin Schmidt ,  Yann Mignot

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/40 ,  H01L29/423

Abstract: Techniques for VFET gate length control are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a substrate; forming first polymer spacers alongside opposite sidewalls of the fins; forming second polymer spacers offset from the fins by the first polymer spacers; removing the first polymer spacers selective to the second polymer spacers; reflowing the second polymer spacers to close a gap to the fins; forming a cladding layer above the second polymer spacers; removing the second polymer spacers; forming gates along opposite sidewalls of the fins exposed in between the bottom spacers and the cladding layer, wherein the gates have a gate length Lg set by removal of the second polymer spacers; forming top spacers above the cladding layer; and forming top source and drains above the top spacers. A VFET device is also provided.

公开(公告)号：US20160379929A1

公开(公告)日：2016-12-29

申请号：US15152981

申请日：2016-05-12

Applicant: International Business Machines Corporation ,  Tokyo Electron Limited ,  STMicroelectronics, Inc.

Inventor： Yannick Feurprier ,  Joe Lee ,  Lars W. Liebmann ,  Yann Mignot ,  Terry A. Spooner ,  Douglas M. Trickett ,  Mehmet Yilmaz

IPC: H01L23/522 ,  H01L21/321 ,  H01L21/033 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L23/5226 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.

Abstract translation: 一种用于在集成电路中形成通孔的方法包括：图案化第一硬掩模中的第一开口，设置在第一有机自平面化聚合物（OPL）层上的第一硬掩模，去除第一OPL层的暴露部分以限定空腔 去除所述空腔中的第二硬掩模的暴露部分，去除设置在所述第二硬掩模下方的第一介电层的暴露部分以进一步限定所述空腔，去除所述空腔中的第一盖层的暴露部分，去除暴露部分 以进一步限定所述空腔，去除第二盖层的暴露部分以进一步限定所述空腔，在所述空腔中的第二导电材料上移除衬里层的暴露部分，以及在所述腔中沉积导电材料 腔。

公开(公告)号：US09373582B1

公开(公告)日：2016-06-21

申请号：US14749140

申请日：2015-06-24

Applicant: International Business Machines Corporation ,  Tokyo Electron Limited ,  STMicroelectronics, Inc.

Inventor： Yannick Feurprier ,  Joe Lee ,  Lars W. Liebmann ,  Yann Mignot ,  Terry A. Spooner ,  Douglas M. Trickett ,  Mehmet Yilmaz

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.

Abstract translation: 用于在集成电路中形成通孔的方法包括：图案化第一硬掩模中的第一开口，设置在第一有机自平面化聚合物（OPL）层上的第一硬掩模，去除第一OPL层的暴露部分以限定空腔 去除所述空腔中的第二硬掩模的暴露部分，去除设置在所述第二硬掩模下方的第一介电层的暴露部分以进一步限定所述空腔，去除所述空腔中的第一盖层的暴露部分，去除暴露部分 以进一步限定所述空腔，去除第二盖层的暴露部分以进一步限定所述空腔，在所述空腔中的第二导电材料上移除衬里层的暴露部分，以及在所述腔中沉积导电材料 腔。

公开(公告)号：US20160172231A1

公开(公告)日：2016-06-16

申请号：US14567567

申请日：2014-12-11

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Joe Lee ,  Yann Mignot ,  Brown C. Peethala

IPC: H01L21/768

CPC classification number: H01L21/7682 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76843

Abstract: A selective wet etching process is used, prior to air gap opening formation, to remove a sacrificial nitride layer from over a first region of an interconnect dielectric material containing a plurality of first conductive metal structures utilizing a titanium nitride hard mask portion located over a second region of the interconnect dielectric material as an etch mask. The titanium nitride hard mask portion located over the second region of the interconnect dielectric material is thereafter removed, again prior to air gap opening formation, utilizing another wet etch process. The wet etching processes are used instead of reactive ion etching.

Abstract translation: 在气隙开口形成之前，使用选择性湿蚀刻工艺，以从包含多个第一导电金属结构的互连电介质材料的第一区域上方除去牺牲氮化物层，所述第一导电金属结构利用位于第二层上的氮化钛硬掩模部分 互连电介质材料的区域作为蚀刻掩模。 此后，在气隙开口形成之前，再次移除位于互连电介质材料的第二区域之上的氮化钛硬掩模部分，利用另一湿蚀刻工艺。 使用湿蚀刻工艺代替反应离子蚀刻。

公开(公告)号：US20150221547A1

公开(公告)日：2015-08-06

申请号：US14172263

申请日：2014-02-04

Applicant: STMICROELECTRONIC, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John C. Arnold ,  Shyng-Tsong Chen ,  Yann Mignot ,  Muthumanickam Sankarapandian ,  Oscar van der Straten ,  Yunpeng Yin

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L21/31144 ,  H01L21/31116 ,  H01L21/76811

Abstract: A stack of an interlevel dielectric (ILD) layer, a dielectric cap layer, and a metallic hard mask layer is formed on a substrate. The metallic hard mask layer can be patterned with a first pattern. A photoresist layer is formed over the metallic hard mask layer and is patterned with a second pattern. A combination of the first pattern and the second pattern is transferred into the ILD layer to form a dual damascene trench, which includes an undercut underneath the patterned dielectric cap layer. The metallic hard mask layer is removed and the dielectric cap layer is anisotropically etched to form faceted edges and removal of overhanging portions. A metallic material can be deposited into the dual damascene trench without formation of voids during a metal fill process.

Abstract translation: 在衬底上形成层间电介质（ILD）层，电介质覆盖层和金属硬掩模层的堆叠。 金属硬掩模层可以用第一图案图案化。 在金属硬掩模层上形成光致抗蚀剂层，并以第二图案形成图案。 将第一图案和第二图案的组合转移到ILD层中以形成双镶嵌沟槽，其包括在图案化电介质盖层下方的底切。 去除金属硬掩模层并且电介质盖层被各向异性地蚀刻以形成刻面边缘和去除突出部分。 金属材料可以在金属填充过程中沉积到双镶嵌槽中而不形成空隙。

公开(公告)号：US20150076707A1

公开(公告)日：2015-03-19

申请号：US14030092

申请日：2013-09-18

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  Tokyo Electron Limited

Inventor： Yann Mignot ,  Yannick Feurprier ,  Wayne Meher

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76816 ,  H01L21/31144 ,  H01L21/76811 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for creating one or more vias in an integrated circuit structure and the integrated circuit structure. The method includes depositing a coating layer over a hard mask layer on the integrated circuit structure; locating an initial via pattern layer over the coating layer; and etching the pattern of the one or more initial openings in the coating layer and through openings in the hard mask layer. The coating layer is a conformal deposition of an oxide, a boron nitride, or other nitride. The initial via pattern layer has one or more initial openings located therein.

Abstract translation: 一种用于在集成电路结构和集成电路结构中创建一个或多个通孔的方法。 该方法包括在集成电路结构上的硬掩模层上沉积涂层; 将初始通孔图案层定位在涂层上; 并且蚀刻涂层中的一个或多个初始开口的图案并且通过硬掩模层中的开口。 涂层是氧化物，氮化硼或其它氮化物的共形沉积。 初始通孔图案层具有位于其中的一个或多个初始开口。

公开(公告)号：US12094774B2

公开(公告)日：2024-09-17

申请号：US17474292

申请日：2021-09-14

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  Yongan Xu ,  Hsueh-Chung Chen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76885 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/5283

Abstract: Embodiments of the present invention are directed to fabrication methods and resulting structures having a back-end-of-line (BEOL) single damascene (SD) top via spacer defined by pillar mandrels. In a non-limiting embodiment of the invention, a first conductive line is formed in a first dielectric layer. A mandrel is formed over the first conductive line and a spacer is formed on a sidewall of the mandrel. A portion of a second dielectric layer is recessed to expose a top surface of the spacer and a top surface of the mandrel and the mandrel is removed. The spacer prevents damage to the second dielectric layer while removing the mandrel. The mandrel is replaced with a conductive material. A first portion of the conductive material defines a via and a second portion of the conductive material defines a second conductive line. The via couples the first conductive line to the second conductive line.

公开(公告)号：US20240282704A1

公开(公告)日：2024-08-22

申请号：US18171795

申请日：2023-02-21

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  Chanro Park ,  Koichi Motoyama ,  John Christopher Arnold

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53257

Abstract: A semiconductor structure is presented including a metal layer having a first pattern, a metal bridge located within the first pattern, at least one via disposed on a portion of the metal layer such that the metal bridge extends to a top surface of the at least one via, and a metal cap disposed directly on top of the at least one via disposed on the portion of the metal layer.