公开(公告)号：US10043782B2

公开(公告)日：2018-08-07

申请号：US15470960

申请日：2017-03-28

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Holger Doepke ,  Olaf Hohlfeld ,  Michael Juerss

IPC: H01L21/56 ,  H01L23/31 ,  H05K3/28 ,  H01L25/07 ,  H01L21/52 ,  H01L23/29 ,  H01L23/552 ,  H01L23/00

Abstract: A method for fabricating an electronic device package includes providing a carrier, disposing a semiconductor chip onto the carrier, the semiconductor chip having a contact pad on a main face thereof remote from the carrier, applying a contact element onto the contact pad, applying a dielectric layer on the carrier, the semiconductor chip, and the contact element, and applying an encapsulant onto the dielectric layer.

公开(公告)号：US09698070B2

公开(公告)日：2017-07-04

申请号：US13860679

申请日：2013-04-11

Applicant: Infineon Technologies AG

Inventor： Michael Ledutke ,  Edward Fuergut

IPC: H01L23/28 ,  H01L23/31 ,  H01L21/66 ,  H01L21/56 ,  H01L21/673

CPC classification number: H01L23/3107 ,  H01L21/561 ,  H01L21/67336 ,  H01L22/10 ,  H01L22/32 ,  H01L23/3121 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In various embodiments, an arrangement is provided. The arrangement may include a plurality of chips; a chip carrier carrying the plurality of chips, the chip carrier including a chip carrier notch; and encapsulation material encapsulating the chip carrier and filling the chip carrier notch; wherein the outer circumference of the encapsulation material is free from a recess.

公开(公告)号：US09627287B2

公开(公告)日：2017-04-18

申请号：US14058213

申请日：2013-10-18

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Edward Fuergut ,  Hannes Eder

IPC: H01L21/762 ,  H01L23/28 ,  H01L21/78 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/28 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76251 ,  H01L21/76254 ,  H01L21/76259 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3185 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a thinned encapsulated chip structure, wherein the method comprises providing a separation structure arranged within an electronic chip, encapsulating part of the electronic chip by an encapsulating structure, and thinning selectively the electronic chip partially encapsulated by the encapsulating structure so that the encapsulating structure remains with a larger thickness than the thinned electronic chip, wherein the separation structure functions as a thinning stop.

公开(公告)号：US09589859B2

公开(公告)日：2017-03-07

申请号：US14462693

申请日：2014-08-19

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Edward Fuergut ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L23/34 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/66 ,  H01L23/522 ,  H01L27/02 ,  H01L23/00 ,  H01L23/051

CPC classification number: H01L21/78 ,  H01L21/4875 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L22/10 ,  H01L22/14 ,  H01L23/051 ,  H01L23/31 ,  H01L23/522 ,  H01L24/96 ,  H01L25/072 ,  H01L25/115 ,  H01L27/02 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor arrangement includes a plurality of chip assemblies, each of which includes a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally circumferentially in a ring-shaped fashion such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.

Abstract translation: 半导体装置包括多个芯片组件，每个芯片组件包括半导体芯片，半导体芯片具有顶侧和下侧的半导体主体，布置在顶侧的顶部主电极，布置在下侧的底部主电极，电气 导电顶部补偿层布置在顶部主电极的背离半导体主体的一侧并且内导电地连接到顶部主电极，导电底部补偿层布置在底部主电极的背离 半导体本体并且内导电地连接到底部主电极，以及环形化方式围绕半导体芯片横向周向的电介质嵌入化合物，使得补偿层的背离半导体本体的一侧至少不是完全的 被包埋化合物覆盖。

公开(公告)号：US09437513B2

公开(公告)日：2016-09-06

申请号：US14501070

申请日：2014-09-30

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Manfred Mengel

IPC: H01L23/31 ,  H01L23/367 ,  H01L21/52 ,  H01L21/56 ,  H01L23/433 ,  H01L23/373

CPC classification number: H01L23/3675 ,  H01L21/3105 ,  H01L21/4871 ,  H01L21/52 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/3737 ,  H01L23/4334 ,  H01L23/49551 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/32013 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/17747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: Method for manufacturing an electronic semiconductor package, in which method an electronic chip (100) is coupled to a carrier, the electronic chip is at least partially encapsulated by means of an encapsulation structure having a discontinuity, and the carrier is partially encapsulated, and at least one part of the discontinuity and a volume connected thereto adjoining an exposed surface section of the carrier are covered by an electrically insulating thermal interface structure, which electrically decouples at least one part of the carrier with respect to its surroundings.

公开(公告)号：US09395404B2

公开(公告)日：2016-07-19

申请号：US13715990

申请日：2012-12-14

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Horst Groeninger

IPC: G01R31/20 ,  G01R31/26

CPC classification number: G01R31/2601

Abstract: A semiconductor chip panel includes a plurality of semiconductor chips embedded in an encapsulation material. At least part of the semiconductor chips comprise a first electrical contact element on a first main face and a second electrical contact element on a second main opposite to the first main face, respectively. One of the plurality of semiconductor chips is tested by establishing an electrical contact between a test contact device and the first electrical contact element and between an electrically conductive holder and the second contact element.

Abstract translation: 半导体芯片面板包括嵌入在封装材料中的多个半导体芯片。 半导体芯片的至少一部分分别包括在第一主面上的第一电接触元件和与第一主面相对的第二主体上的第二电接触元件。 通过在测试接触装置和第一电接触元件之间以及在导电保持器和第二接触元件之间建立电接触来测试多个半导体芯片中的一个。

公开(公告)号：US20160181138A1

公开(公告)日：2016-06-23

申请号：US14757589

申请日：2015-12-23

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Edward Fuergut ,  Joachim Mahler

IPC: H01L21/683 ,  H01L21/768 ,  H01L21/56 ,  H01L23/528 ,  H01L21/78

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/94 ,  H01L24/96 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/94 ,  H01L2224/83

Abstract: Various embodiments provide method of manufacturing a semiconductor component, wherein the method comprises providing a layer stack comprising a carrier and a thinned wafer comprising a metallization layer on one side, wherein the thinned wafer is placed on a first side of the carrier; forming an encapsulation encapsulating the layer stack at least partially; and subsequently thinning the carrier from a second side of the carrier, wherein the second side is opposite to the first side of the carrier.

Abstract translation: 各种实施例提供制造半导体部件的方法，其中所述方法包括提供包括载体的层堆叠和在一侧上包括金属化层的薄化晶片，其中所述薄化晶片被放置在所述载体的第一侧上; 至少部分地形成封装所述层堆叠的封装; 随后从所述载体的第二侧使所述载体变薄，其中所述第二侧与所述载体的第一侧相对。

公开(公告)号：US09064869B2

公开(公告)日：2015-06-23

申请号：US13974583

申请日：2013-08-23

Applicant: Infineon Technologies AG

Inventor： Juergen Hoegerl ,  Edward Fuergut ,  Gottfried Beer ,  Olaf Hohlfeld

IPC: H01L23/18 ,  H01L21/60 ,  H01L23/522 ,  H01L23/00 ,  H01L23/28 ,  H01L23/31 ,  H01L23/485 ,  H01L25/18 ,  H01L27/12

CPC classification number: H01L23/5226 ,  H01L21/561 ,  H01L21/568 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3735 ,  H01L23/485 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/09 ,  H01L24/24 ,  H01L24/29 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/89 ,  H01L24/92 ,  H01L25/18 ,  H01L27/12 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2413 ,  H01L2224/24137 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/92244 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014

Abstract: The semiconductor module includes a carrier, a plurality of semiconductor transistor chips disposed on the carrier, a plurality of semiconductor diode chips disposed on the carrier, an encapsulation layer disposed above the semiconductor transistor chips and the semiconductor diode chips, and a metallization layer disposed above the encapsulation layer. The metallization layer includes a plurality of metallic areas forming electrical connections between selected ones of the semiconductor transistor chips and the semiconductor diode chips.

Abstract translation: 半导体模块包括载体，设置在载体上的多个半导体晶体管芯片，设置在载体上的多个半导体二极管芯片，设置在半导体晶体管芯片和半导体二极管芯片上方的封装层以及设置在半导体二极管芯片上方的金属化层 封装层。 金属化层包括形成半导体晶体管芯片中选定的半导体晶体管芯片和半导体二极管芯片之间的电连接的多个金属区域。

公开(公告)号：US20150054166A1

公开(公告)日：2015-02-26

申请号：US14462693

申请日：2014-08-19

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Edward Fuergut ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L23/31 ,  H01L21/66 ,  H01L21/56 ,  H01L21/78 ,  H01L27/02 ,  H01L23/522

CPC classification number: H01L21/78 ,  H01L21/4875 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L22/10 ,  H01L22/14 ,  H01L23/051 ,  H01L23/31 ,  H01L23/522 ,  H01L24/96 ,  H01L25/072 ,  H01L25/115 ,  H01L27/02 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor arrangement includes a plurality of chip assemblies, each of which includes a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally circumferentially in a ring-shaped fashion such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.

Abstract translation: 半导体装置包括多个芯片组件，每个芯片组件包括半导体芯片，半导体芯片具有顶侧和下侧的半导体主体，布置在顶侧的顶部主电极，布置在下侧的底部主电极，电气 导电顶部补偿层布置在顶部主电极的背离半导体主体的一侧并且内导电地连接到顶部主电极，导电底部补偿层布置在底部主电极的背离 半导体本体并且内导电地连接到底部主电极，以及环形化方式围绕半导体芯片横向周向的电介质嵌入化合物，使得补偿层的背离半导体本体的一侧至少不是完全的 被包埋化合物覆盖。

公开(公告)号：US20140151862A1

公开(公告)日：2014-06-05

申请号：US14151917

申请日：2014-01-10

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Edward Fuergut ,  Khalil Hosseini ,  Georg Meyer-Berg

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2924/00

Abstract: A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects.