公开(公告)号：US20180074969A1

公开(公告)日：2018-03-15

申请号：US15260893

申请日：2016-09-09

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Baiju V. Patel ,  Gur Hildesheim ,  Ron Rais ,  Andrew V. Anderson ,  Jason W. Brandt ,  David M. Durham ,  Barry E. Huntley ,  Raanan Sade ,  Ravi L. Sahita ,  Vedvyas Shanbhogue ,  Arumugam Thiyagarajah

IPC: G06F12/1009 ,  G06F12/14 ,  G06F9/455

CPC classification number: G06F12/1009 ,  G06F9/45545 ,  G06F9/45558 ,  G06F12/1441 ,  G06F12/145 ,  G06F12/1491 ,  G06F2009/45583 ,  G06F2009/45587 ,  G06F2212/151 ,  G06F2212/651

Abstract: A processing system includes a processing core to execute a virtual machine (VM) comprising a guest operating system (OS) and a memory management unit, communicatively coupled to the processing core, comprising a storage device to store an extended page table entry (EPTE) comprising a mapping from a guest physical address (GPA) associated with the guest OS to an identifier of a memory frame, a first plurality of access right flags associated with accessing the memory frame in a first page mode referenced by an attribute of a memory page identified by the GPA, and a second plurality of access right flags associated with accessing the memory frame in a second page mode referenced by the attribute of the memory page identified by the GPA.

公开(公告)号：US20180060247A1

公开(公告)日：2018-03-01

申请号：US15620663

申请日：2017-06-12

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

IPC: G06F12/02 ,  G06F9/455

CPC classification number: G06F12/1027 ,  G06F9/30047 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US09678890B2

公开(公告)日：2017-06-13

申请号：US14867025

申请日：2015-09-28

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard A Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

IPC: G06F12/10 ,  G06F12/1027 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/02 ,  G06F9/455 ,  G06F12/0875 ,  G06F12/1045

CPC classification number: G06F12/1027 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US20170132128A1

公开(公告)日：2017-05-11

申请号：US15411658

申请日：2017-01-20

Applicant: Intel Corporation

Inventor： Sanjay Kumar ,  Rajesh M. Sankaran ,  Subramanya R. Dulloor ,  Andrew V. Anderson

IPC: G06F12/0804 ,  G06F11/14

CPC classification number: G06F12/0804 ,  G06F9/467 ,  G06F11/07 ,  G06F11/073 ,  G06F11/0778 ,  G06F11/0793 ,  G06F11/14 ,  G06F11/1482 ,  G06F12/0868 ,  G06F2201/805 ,  G06F2201/82 ,  G06F2212/1032 ,  G06F2212/608

Abstract: A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction. The memory management unit includes logic to, based upon a flush-on-fail (FoF) mode, skip execution of the flush-on-commit instruction and to flush the dirty data from the volatile cache upon a subsequent FoF operation.

公开(公告)号：US20170052832A1

公开(公告)日：2017-02-23

申请号：US15226864

申请日：2016-08-02

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Dion Rodgers ,  Richard A. Uhlig ,  Lawrence O. Smith ,  Barry E. Huntley

IPC: G06F9/54 ,  G06F9/48 ,  G06F9/455

CPC classification number: G06F9/45533 ,  G06F9/3861 ,  G06F9/45545 ,  G06F9/4555 ,  G06F9/45558 ,  G06F9/4812 ,  G06F9/542 ,  G06F13/24 ,  G06F2009/45566

Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a hardware processor including event circuit to recognize a virtualization event, and evaluation circuit to determine whether to transfer control of the apparatus from a child guest to a parent guest in response to the virtualization event, wherein the child guest and the parent guest each include a bit per virtualization event to indicate whether the parent guest is to gain control when the virtualization event occurs.

Abstract translation: 公开了在分层虚拟化架构中处理虚拟化事件的装置和方法的实施例。 在一个实施例中，一种装置包括硬件处理器，包括用于识别虚拟化事件的事件电路，以及评估电路，用于响应虚拟化事件确定是否将该设备的控制从子客户转移到父访客，其中，该子客户机 并且父客户每个包含一个虚拟化事件，以指示在虚拟化事件发生时父访客是否获得控制。

公开(公告)号：US20160170645A1

公开(公告)日：2016-06-16

申请号：US14567662

申请日：2014-12-11

Applicant: Intel Corporation

Inventor： Sanjay Kumar ,  Rajesh M. Sankaran ,  Subramanya R. Dulloor ,  Dheeraj R. Subbareddy ,  Andrew V. Anderson

IPC: G06F3/06

CPC classification number: G06F12/0842 ,  G06F12/0238 ,  G06F12/06 ,  G06F12/0897 ,  G06F12/1009 ,  G06F2212/225 ,  G06F2212/601 ,  G06F2212/7201

Abstract: Computer-readable storage media, computing apparatuses and methods associated with persistent memory are discussed herein. In embodiments, a computing apparatus may include one or more processors, along with a plurality of persistent storage modules that may be coupled with the one or more processors. The computing apparatus may further include system software, to be operated by the one or more processors, to receive volatile memory allocation requests and persistent storage allocation requests from one or more applications that may be executed by the one or more processors. The system software may then dynamically allocate memory pages of the persistent storage modules as: volatile type memory pages, in response to the volatile memory allocation requests, and persistent type memory pages, in response to the persistent storage allocation requests. Other embodiments may be described and/or claimed.

Abstract translation: 本文讨论了与永久存储器相关联的计算机可读存储介质，计算设备和方法。 在实施例中，计算设备可以包括一个或多个处理器，以及可以与一个或多个处理器耦合的多个持久存储模块。 计算设备还可以包括由一个或多个处理器操作的系统软件，以从一个或多个处理器执行的一个或多个应用接收易失性存储器分配请求和持久存储分配请求。 然后，响应于持久存储分配请求，系统软件可以响应于易失性存储器分配请求和持久类型存储器页面动态分配持久存储模块的存储器页面：易失性存储器页面。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09335943B2

公开(公告)日：2016-05-10

申请号：US14320334

申请日：2014-06-30

Applicant: Intel Corporation

Inventor： Ravi L. Sahita ,  Vedvyas Shanbhogue ,  Gilbert Neiger ,  Jonathan Edwards ,  Ido Ouziel ,  Barry E. Huntley ,  Stanislav Shwartsman ,  David M. Durham ,  Andrew V. Anderson ,  Michael Lemay

IPC: G06F21/00 ,  G06F3/06 ,  G06F12/10 ,  G06F9/455

CPC classification number: G06F9/45558 ,  G06F9/3004 ,  G06F9/30076 ,  G06F12/1009 ,  G06F2009/45583 ,  G06F2212/657

Abstract: An apparatus and method for fine grain memory protection. For example, one embodiment of a method comprises: performing a first lookup operation using a virtual address to identify a physical address of a memory page, the memory page comprising a plurality of sub-pages; determining whether sub-page permissions are enabled for the memory page; if sub-page permissions are enabled, then performing a second lookup operation to determine permissions associated with one or more of the sub-pages of the memory page; and implementing the permissions associated with the one or more sub-pages.

Abstract translation: 一种细粒度记忆保护装置和方法。 例如，方法的一个实施例包括：使用虚拟地址执行第一查找操作以识别存储器页面的物理地址，所述存储器页面包括多个子页面; 确定是否为所述存储器页启用子页面许可; 如果启用子页面许可，则执行第二查找操作以确定与存储器页面的一个或多个子页面相关联的许可; 以及实现与一个或多个子页面相关联的许可。

公开(公告)号：US20160019165A1

公开(公告)日：2016-01-21

申请号：US14867024

申请日：2015-09-28

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard A. Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

IPC: G06F12/10 ,  G06F12/02 ,  G06F12/08

CPC classification number: G06F12/1027 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US09164920B2

公开(公告)日：2015-10-20

申请号：US14569069

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Rajesh Sankaran Madukkarumukumana ,  Richard UhligQ ,  Lawrence Smith, III ,  Scott D. Rodgers

IPC: G06F12/10 ,  G06F9/455 ,  G06F12/14

CPC classification number: G06F12/1483 ,  G06F9/45533 ,  G06F9/45558 ,  G06F12/109 ,  G06F2009/45583 ,  G06F2212/151 ,  G06F2212/152 ,  G06F2212/657

Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

Abstract translation: 一种处理器，其包括具有存储器虚拟化支持系统的处理器的虚拟化系统，以将参考映射到由虚拟机上可执行的客户机软件制成的客体物理存储器，该虚拟机器又可在主机上执行，其中处理器可操作为 引用主机的主机物理内存。

公开(公告)号：US09122624B2

公开(公告)日：2015-09-01

申请号：US14517849

申请日：2014-10-18

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard Uhlig ,  Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

IPC: G06F12/00 ,  G06F12/10

CPC classification number: G06F12/1027 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Abstract translation: 一种处理器，包括执行指令以使来自基于虚拟化的系统的客户机的物理地址（客户物理地址）到基于虚拟化系统的主机的物理地址（主机物理地址）的映射同步的指令，并且存储在 翻译后备缓冲器（TLB），其中相应的映射存储在基于虚拟化的系统的扩展分页表（EPT）中。