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268 条记录 (耗时 0.033 秒)

    Method of forming connection and anti-fuse in layered substrate such as SOI
    53.
    发明授权
    Method of forming connection and anti-fuse in layered substrate such as SOI 有权
    在诸如SOI的层状衬底中形成连接和反熔丝的方法

    公开(公告)号：US07226816B2

    公开(公告)日：2007-06-05

    申请号：US11055106

    申请日：2005-02-11

    申请人： Claude L. Bertin ,  Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  William R. Tonti

    发明人： Claude L. Bertin ,  Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  William R. Tonti

    IPC分类号： H01L21/82

    CPC分类号： H01L23/5252 ,  H01L27/10829 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.

    摘要翻译： 可以在低电压和电流下被编程并且潜在地消耗很少的芯片空间并且可以间隙地在间隔最小光刻特征尺寸的元件之间形成的抗熔丝结构形成在复合衬底上，例如绝缘体上硅 通过蚀刻通过绝缘体的接触到支撑半导体层，优选结合形成到达或支撑层的电容器状结构。 反熔丝可以由导体形成的选定位置和/或损坏电容器状结构的电介质来编程。 绝缘环用于围绕导体或电容器状结构的一部分，以将损伤限制在所需位置。 由于编程电流导致的加热效应电压和噪声被有效地隔离到体硅层，从而允许在器件正常工作期间进行编程。 因此实现了自动修复而不中断操作的可能性。

    Method of creating deep trench capacitor using a P+ metal electrode
    54.
    发明授权
    Method of creating deep trench capacitor using a P+ metal electrode 失效
    使用P +金属电极制造深沟槽电容器的方法

    公开(公告)号：US06909137B2

    公开(公告)日：2005-06-21

    申请号：US10249406

    申请日：2003-04-07

    申请人： Ramachandra Divakaruni ,  Jack A. Mandelman ,  Dae-Gyu Park

    发明人： Ramachandra Divakaruni ,  Jack A. Mandelman ,  Dae-Gyu Park

    IPC分类号： H01L21/20 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/10864

    摘要： The present invention comprises a method including the steps of providing a substrate; forming a trench in the substrate; forming a buried plate in the substrate about the trench; depositing a dielectric layer within the trench; and then depositing a P-type metal atop the dielectric layer, where the dielectric layer is positioned between the P-type metal and the buried plate. Another aspect of the present invention provides a trench capacitor where said trench capacitor comprises a trench formed in a substrate, a buried plate formed in the substrate about the trench; a node dielectric; and a P-type metal liner deposited within the trench, where the P-type metal liner is separated from the buried plate by the node dielectric. A P-type metal is defined as a metal having a work function close to the Si valence band, approximately equal to 5.1 eV.

    摘要翻译： 本发明包括一种方法，包括提供基底的步骤; 在衬底中形成沟槽; 在沟槽周围形成衬底; 在沟槽内沉积介电层; 然后在电介质层的顶部沉积P型金属，其中电介质层位于P型金属和掩埋板之间。 本发明的另一方面提供一种沟槽电容器，其中所述沟槽电容器包括形成在衬底中的沟槽，在衬底周围形成的掩埋板围绕沟槽; 节点电介质; 以及沉积在沟槽内的P型金属衬垫，其中P型金属衬垫通过节点电介质与掩埋板分离。 P型金属被定义为具有接近于Si价带的功函数的金属，大约等于5.1eV。

    Method of fabricating a patterened SOI embedded DRAM/eDRAM having a vertical device cell and device formed thereby
    55.
    发明授权
    Method of fabricating a patterened SOI embedded DRAM/eDRAM having a vertical device cell and device formed thereby 有权
    制造具有由此形成的垂直器件单元和器件的平板SOI嵌入式DRAM / eDRAM的方法

    公开(公告)号：US06750097B2

    公开(公告)日：2004-06-15

    申请号：US10210632

    申请日：2002-07-30

    申请人： Ramachandra Divakaruni ,  Jack A. Mandelman

    发明人： Ramachandra Divakaruni ,  Jack A. Mandelman

    IPC分类号： H01L218242

    CPC分类号： H01L27/10897 ,  H01L27/10864 ,  H01L27/1203

    摘要： Disclosed herein is a patterned silicon-on-insulator (SOI) method of fabricating a combined integrated circuit having both a logic portion and an embedded dynamic random access memory (DRAM) array portion. The disclosed method includes masking an array portion of a substrate with a first mask, implanting oxygen to form a buried oxide layer in a logic portion of the substrate not masked by the first mask, depositing and patterning a second mask over the array portion and the logic portion, and etching isolation trenches in the array portion and the logic portion, the isolation trenches defined by openings in the patterned second mask. The first mask may additionally protect the array portion when rounding device corners in the logic portion. The second mask may additionally protect the logic portion when performing implants in the array portion. An integrated circuit formed on a single substrate is disclosed herein including at least one SOI device having a rounded corner and at least one DRAM cell having a vertical pass gate, wherein the DRAM cell is formed on a bulk portion of the substrate.

    摘要翻译： 本文公开了一种制造具有逻辑部分和嵌入式动态随机存取存储器（DRAM）阵列部分的组合集成电路的图案化的绝缘体上硅（SOI）方法。 所公开的方法包括用第一掩模掩蔽衬底的阵列部分，注入氧以在未被第一掩模掩蔽的衬底的逻辑部分中形成掩埋氧化物层，在阵列部分上沉积和图案化第二掩模， 逻辑部分和在阵列部分和逻辑部分中的蚀刻隔离沟槽，隔离沟槽由图案化的第二掩模中的开口限定。 当对逻辑部分中的设备角进行舍入时，第一掩模可以附加地保护阵列部分。 当在阵列部分中执行植入时，第二掩模可以附加地保护逻辑部分。 本文公开了形成在单个基板上的集成电路，其包括具有圆角的至少一个SOI器件和具有垂直通过栅极的至少一个DRAM单元，其中所述DRAM单元形成在所述衬底的主体部分上。

    Asymmetric inside spacer for vertical transistor
    56.
    发明授权
    Asymmetric inside spacer for vertical transistor 失效
    垂直晶体管的不对称内隔板

    公开(公告)号：US06642566B1

    公开(公告)日：2003-11-04

    申请号：US10195601

    申请日：2002-06-28

    申请人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Haining Yang

    发明人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Haining Yang

    IPC分类号： H01L2708

    CPC分类号： H01L27/10876 ,  H01L27/10864 ,  H01L27/10888 ,  H01L27/10891

    摘要： A DRAM array having a DRAM cell employing vertical transistors increases electrical reliability and reduces bitline capacitance by use of an asymmetric structure in the connection between the wordline and the transistor, thereby permitting the use of a wider connection between the wordline and the transistor electrode and using the wordline as an etch stop to protect the transistor gate during the patterning of the wordlines.

    摘要翻译： 具有使用垂直晶体管的DRAM单元的DRAM阵列通过在字线和晶体管之间的连接中使用不对称结构来增加电可靠性并降低位线电容，从而允许在字线和晶体管电极之间使用更宽的连接并且使用 该字线作为蚀刻停止以在图形化字线期间保护晶体管栅极。

    Method for novel SOI DRAM BICMOS NPN
    58.
    发明授权
    Method for novel SOI DRAM BICMOS NPN 失效
    新型SOI DRAM BICMOS NPN的方法

    公开(公告)号：US06492211B1

    公开(公告)日：2002-12-10

    申请号：US09656819

    申请日：2000-09-07

    申请人： Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  W. David Pricer ,  William R. Tonti

    发明人： Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  W. David Pricer ,  William R. Tonti

    IPC分类号： H01L2100

    CPC分类号： H01L27/10894 ,  G11C7/065 ,  G11C2207/005 ,  G11C2207/065 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/10897 ,  H01L27/1203

    摘要： There is disclosed herein a unique fabrication sequence and the structure of a vertical silicon on insulator (SOI) bipolar transistor integrated into a typical DRAM trench process sequence. A DRAM array utilizing an NFET allows for an integrated bipolar NPN sequence. Similarly, a vertical bipolar PNP device is implemented by changing the array transistor to a PFET. Particularly, a BICMOS device is fabricated in SOI. The bipolar emitter contacts and CMOS diffusion contacts are formed simultaneously of polysilicon plugs. The CMOS diffusion contact is the plug contact from bitline to storage node of a memory cell.

    摘要翻译： 在此公开了独特的制造顺序和集成到典型的DRAM沟槽工艺序列中的垂直绝缘体上硅（SOI）双极晶体管的结构。 使用NFET的DRAM阵列允许集成双极NPN序列。 类似地，通过将​​阵列晶体管改变为PFET来实现垂直双极PNP器件。 特别地，在SOI中制造BICMOS器件。 双极发射极触点和CMOS扩散触点同时形成多晶硅插头。 CMOS扩散触点是从存储单元的位线到存储节点的插头触点。

    Bitline diffusion with halo for improved array threshold voltage control
    59.
    发明授权
    Bitline diffusion with halo for improved array threshold voltage control 有权

    公开(公告)号：US06444548B1

    公开(公告)日：2002-09-03

    申请号：US09257817

    申请日：1999-02-25

    申请人： Ramachandra Divakaruni ,  Yujun Li ,  Jack A. Mandelman

    发明人： Ramachandra Divakaruni ,  Yujun Li ,  Jack A. Mandelman

    IPC分类号： H01L218242

    摘要： A integrated circuit device and method for manufacturing an integrated circuit device includes forming a patterned gate stack, adjacent a storage device, to include a storage node diffusion region adjacent the storage device and a bitline contact diffusion region opposite the storage node diffusion region, implanting an impurity in the storage node diffusion region and the bitline contact diffusion region, forming an insulator layer over the patterned gate stack, removing a portion of the insulator layer from the bitline contact diffusion region to form sidewall spacers along a portion of the patterned gate stack adjacent the bitline contact diffusion region, implanting a halo implant into the bitline contact diffusion region, wherein the insulator layer is free from blocking the halo implant from the second diffusion region and annealing the integrated circuit device to drive the halo implant ahead of the impurity.