公开(公告)号：US07902930B2

公开(公告)日：2011-03-08

申请号：US11927957

申请日：2007-10-30

申请人： Ja Yol Lee ,  Sang Heung Lee ,  Hyun Kyu Yu

发明人： Ja Yol Lee ,  Sang Heung Lee ,  Hyun Kyu Yu

IPC分类号： H03K3/03

CPC分类号： H03B5/1218 ,  H03B5/1231 ,  H03B2200/0074 ,  H03B2200/0078

摘要： Provided is a colpitts quadrature voltage controlled oscillator capable of obtaining quadrature orthogonal signals using a quadrature combination between a base and a collector of each transistor, without using an additional circuit such as a coupled transistor, a coupled transformer, a multiphase RC filter, etc. Accordingly, since nonlinearity, increased phase noise, a decrease in the Q-factor of an LC resonator, and increased power consumption can be avoided, a colpitts quadrature voltage controlled oscillator that has low phase noise, low electric power consumption, and a compact size can be implemented.

摘要翻译： 提供了一种能够在不使用诸如耦合晶体管，耦合变压器，多相RC滤波器等附加电路的情况下使用每个晶体管的基极和集电极之间的正交组合获得正交正交信号的绞合正交压控振荡器。 因此，由于可以避免非线性，增加的相位噪声，LC谐振器的Q因子的降低和功率消耗的增加，所以抑制相位噪声低，功耗低，尺寸紧凑的正交压控振荡器 可以实现。

公开(公告)号：US20100134334A1

公开(公告)日：2010-06-03

申请号：US12628186

申请日：2009-11-30

申请人： Jae Hoon SHIM ,  Hyun Kyu Yu

发明人： Jae Hoon SHIM ,  Hyun Kyu Yu

IPC分类号： H03M1/06

CPC分类号： H03F3/005

摘要： There is provided a digital Direct Current (DC) offset correction method and device. The device includes a digital-analog converter charging a load capacitor according to an input code value and generating an initial voltage value of the load capacitor; a comparator comparing an output DC offset value of a discrete-time amplifier and filter on the basis of the initial voltage value with a preset output DC offset value when the discrete-time amplifier and filter and the load capacitor are connected to each other; and a controller changing the input code value of the digital-analog converter according to comparison result of the comparator.

摘要翻译： 提供了数字直流（DC）偏移校正方法和装置。 该装置包括数模转换器，根据输入代码值对负载电容器充电并产生负载电容器的初始电压值; 当离散时间放大器和滤波器和负载电容器彼此连接时，比较器将基于初始电压值的离散时间放大器和滤波器的输出DC偏移值与预设输出DC偏移值进行比较; 以及根据比较器的比较结果改变数模转换器的输入代码值的控制器。

公开(公告)号：US07626476B2

公开(公告)日：2009-12-01

申请号：US11690219

申请日：2007-03-23

申请人： Cheon Soo Kim ,  Myung Shin Kwak ,  Seong Do Kim ,  Mun Yang Park ,  Hyun Kyu Yu ,  Hee Bum Jung

发明人： Cheon Soo Kim ,  Myung Shin Kwak ,  Seong Do Kim ,  Mun Yang Park ,  Hyun Kyu Yu ,  Hee Bum Jung

IPC分类号： H01P3/08

CPC分类号： H01P3/003

摘要： A coplanar waveguide CPW using multi-layer interconnection CMOS technology is provided. In the CPW including an interlayer insulator disposed on a substrate, metal multilayers disposed on the interlayer insulator, and a ground line-a signal line-a ground line formed of an uppermost metal layer, when a ground line of a lowermost layer is connected to the ground line of the uppermost layer, intermediate metal layers are designed to gradually increase or decrease in width, or to be uneven so as to maximize an area where an ultra-high frequency spreads, thereby minimizing CPW loss and maximizing a slow wave effect. As a result, it is possible to improve performance of an ultra-high frequency circuit and miniaturize the circuit.

摘要翻译： 提供了一种使用多层互连CMOS技术的共面波导CPW。 在包括设置在基板上的层间绝缘体的CPW中，设置在层间绝缘体上的金属多层和最下层的接地线的接地线 - 信号线 - 由最上层金属层形成的接地线连接到 最上层的地线，中间金属层被设计成逐渐增加或减小宽度或不均匀，以便使超高频率扩展的面积最大化，由此最小化CPW损耗并最大化慢波效应。 结果，可以提高超高频电路的性能并使电路小型化。

公开(公告)号：US20090261481A1

公开(公告)日：2009-10-22

申请号：US12208512

申请日：2008-09-11

申请人： Jong Tae MOON ,  Yong Sung Eom ,  Min Ji Lee ,  Hyun Kyu Yu

发明人： Jong Tae MOON ,  Yong Sung Eom ,  Min Ji Lee ,  Hyun Kyu Yu

IPC分类号： H01L23/52 ,  H01L21/66 ,  H01L21/00

CPC分类号： H01L23/10 ,  B81B7/007 ,  B81C2203/0118 ,  H01L24/45 ,  H01L24/48 ,  H01L24/94 ,  H01L2224/16145 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1461 ,  H01L2924/16235 ,  H01L2924/00 ,  H01L2924/2076 ,  H01L2224/05599

摘要： Provided are a wafer level package in which a communication line can be readily formed between an internal device and the outside of the package, and a method of fabricating the wafer level package. The wafer level package includes a first substrate having a cavity in which a first internal device is disposed, an Input/Output (I/O) pad formed on the first substrate and electrically connected with the first internal device, a second substrate disposed over the first substrate and from which a part corresponding to the I/O pad is removed, and a solder bonding the first and second substrates. According to the wafer level package and the method of fabricating the same, upper and lower substrates are sawed to different cutting widths, or a hole is formed in the upper substrate, such that a communication line of an internal device can be readily formed without a via process which penetrates a substrate. Therefore, in comparison with a conventional wafer level package fabricated using the via process, it is possible to simplify a fabrication process and reduce production cost.

摘要翻译： 提供了一种晶片级封装，其中可以容易地在内部器件和封装外部之间形成通信线，以及制造晶片级封装的方法。 晶片级封装包括具有第一内部器件的空腔的第一衬底，形成在第一衬底上并与第一内部器件电连接的输入/输出（I / O）焊盘，设置在第一衬底上的第二衬底 第一衬底并且从其中除去对应于I / O焊盘的部分，以及焊接第一和第二衬底的焊料。 根据晶片级封装及其制造方法，上下基板被切割成不同的切割宽度，或者在上基板上形成孔，使得可以容易地形成内部装置的连通线，而不需要 穿过基底的过程。 因此，与使用通孔工艺制造的常规晶片级封装相比，可以简化制造工艺并降低生产成本。

公开(公告)号：US20080129392A1

公开(公告)日：2008-06-05

申请号：US11927957

申请日：2007-10-30

申请人： Ja Yol Lee ,  Sang Heung Lee ,  Hyun Kyu Yu

发明人： Ja Yol Lee ,  Sang Heung Lee ,  Hyun Kyu Yu

IPC分类号： H03B27/00 ,  H03B5/12

CPC分类号： H03B5/1218 ,  H03B5/1231 ,  H03B2200/0074 ,  H03B2200/0078

摘要： Provided is a colpitts quadrature voltage controlled oscillator capable of obtaining quadrature orthogonal signals using a quadrature combination between a base and a collector of each transistor, without using an additional circuit such as a coupled transistor, a coupled transformer, a multiphase RC filter, etc. Accordingly, since nonlinearity, increased phase noise, a decrease in the Q-factor of an LC resonator, and increased power consumption can be avoided, a colpitts quadrature voltage controlled oscillator that has low phase noise, low electric power consumption, and a compact size can be implemented.

摘要翻译： 提供了一种能够在不使用诸如耦合晶体管，耦合变压器，多相RC滤波器等附加电路的情况下使用每个晶体管的基极和集电极之间的正交组合获得正交正交信号的绞合正交压控振荡器。 因此，由于可以避免非线性，增加的相位噪声，LC谐振器的Q因子的降低和功率消耗的增加，所以抑制相位噪声低，功耗低，尺寸紧凑的正交压控振荡器 可以实现。

公开(公告)号：US20070134852A1

公开(公告)日：2007-06-14

申请号：US11523212

申请日：2006-09-19

申请人： Sang Jin Byun ,  Hyun Kyu Yu

发明人： Sang Jin Byun ,  Hyun Kyu Yu

IPC分类号： H01L21/82

CPC分类号： H01L27/0207

摘要： Provided are a layout method of a power line for a semiconductor integrated circuit and a semiconductor integrated circuit manufactured by the layout method. The layout method includes the steps of: forming a decoupling capacitor on a substrate; laying out a first metal layer, connected to the decoupling capacitor through a contact, above a region where the decoupling capacitor is formed so as to cover the decoupling capacitor; and laying out a second metal layer above a region where the first metal layer is formed. Therefore, the metal layers and the decoupling capacitor are laid out in the same region so that a chip area can be prevented from being additionally consumed at the time of laying out the decoupling capacitor, and degradation which may occur due to connection line resistance from the power lines to the decoupling capacitors can be prevented.

摘要翻译： 提供了一种用于半导体集成电路的电力线的布局方法和通过布局方法制造的半导体集成电路。 布局方法包括以下步骤：在衬底上形成去耦电容器; 在形成去耦电容器的区域上方布置第一金属层，其通过接触件连接到去耦电容器，以覆盖去耦电容器; 并在其上形成第一金属层的区域上方布置第二金属层。 因此，金属层和去耦电容器布置在相同的区域中，使得在布置去耦电容器时可以防止芯片面积额外消耗，并且可能由于连接线电阻而导致的劣化 可以防止到去耦电容器的电源线。

公开(公告)号：US06668035B2

公开(公告)日：2003-12-23

申请号：US10179840

申请日：2002-06-24

申请人： Seon Ho Han ,  Jang Hong Choi ,  Jae Hong Jang ,  Hyun Kyu Yu

发明人： Seon Ho Han ,  Jang Hong Choi ,  Jae Hong Jang ,  Hyun Kyu Yu

IPC分类号： H03K2100

CPC分类号： H03M7/3022 ,  H03L7/1978

摘要： The present invention relates to a structure of a delta-sigma fractional type divider. The divider structure adds an external input value and an output value of a delta-sigma modulator to modulate a value of a swallow counter. Therefore, the present invention can provide a delta-sigma fractional type divider the structure is simple and that can obtain an effect of a structure of a delta sigma mode while having a wide-band frequency mixing capability.

摘要翻译： 本发明涉及一种delta-sigma分数型分频器的结构。 分频器结构增加了Δ-Σ调制器的外部输入值和输出值，以调制吞咽计数器的值。 因此，本发明可以提供一种Δ-Σ分数分频器，其结构简单，并且可以获得具有宽带频率混合能力的Δ-Σ模式的结构的效果。

公开(公告)号：US06473595B1

公开(公告)日：2002-10-29

申请号：US09437312

申请日：1999-11-10

申请人： Chung Hwan Kim ,  Cheon Soo Kim ,  Hyun Kyu Yu ,  Min Park ,  Dae Yong Kim

发明人： Chung Hwan Kim ,  Cheon Soo Kim ,  Hyun Kyu Yu ,  Min Park ,  Dae Yong Kim

IPC分类号： H04B110

CPC分类号： H03F1/223 ,  H03F1/3205 ,  H03F1/3223

摘要： The RF active balun circuit for improving a small-signal linearity in a power amplifying circuit of a CDMA system is provided under the construction of a signal amplifier driven by exterior individual direct current gate power VGG1, VGG2, for receiving a communication input signal AC-In and performing a cascode amplification at a normal operation point where a feedback third-order distortion signal becomes large; a distortion signal generator driven by exterior direct current gate power VGG3 different from the above power, for generating the communication input signal AC-In as the third-order distortion signal by nonlinearity of an active element to cancel the third-order distortion signal amplified in the signal amplifier; and an insulator provided for an insulation from a exterior driving power VGG3 applied to the distortion signal generator, thereby maintaining the small size, lower power and high efficient terminal characteristics by using a gain based on gate voltage of FET and the nonlinearity characteristic difference, and improving the linearity of an IC operating by a small signal or medium signal.

摘要翻译： 用于改善CDMA系统的功率放大电路中的小信号线性度的RF有源平衡 - 不平衡转换器被提供在由外部单独的直流栅极功率VGG1，VGG2驱动的信号放大器的构造下，用于接收通信输入信号AC- 在反馈三阶失真信号变大的正常工作点进行并进行共源共栅放大; 由与上述功率不同的外部直流栅极功率VGG3驱动的失真信号发生器，用于通过有源元件的非线性产生作为三阶失真信号的通信输入信号AC-In，以消除放大的三阶失真信号 信号放大器; 以及提供用于与施加到失真信号发生器的外部驱动电力VGG3绝缘的绝缘体，从而通过使用基于FET的栅极电压的增益和非线性特性差来维持小尺寸，较低功率和高效率的端子特性，以及 改善由小信号或中等信号操作的IC的线性度。

公开(公告)号：US6093599A

公开(公告)日：2000-07-25

申请号：US232691

申请日：1999-01-19

申请人： Jin Hyo Lee ,  Heung Soo Rhee ,  Hyun Kyu Yu ,  Bo Woo Kim ,  Kee Soo Nam

发明人： Jin Hyo Lee ,  Heung Soo Rhee ,  Hyun Kyu Yu ,  Bo Woo Kim ,  Kee Soo Nam

IPC分类号： H01L21/76 ,  H01L21/763 ,  H01L21/822 ,  H01L27/04 ,  H01L27/08 ,  H01L21/8234

CPC分类号： H01L21/763 ,  H01L27/08

摘要： The present invention relates to a on silicon substrate, specifically to an inductor device and manufacturing method thereof for enhancing the quality factor of the inductor by disposing trenches on a silicon substratre, and by filling the inside of the trenches with polycrystalline polysilicon not doped with impurities. The present invention provides an inductor device and a manufacturing method thereof which can improve the quality factor by increasing resistance of the substrate by forming deep trenches disposed in specific patterns on a low-resistance silicon substrate and filling polycrystalline silicon not doped with impurities, and by reducing parasitic capacitance between the inductor and the silicon substrate.

摘要翻译： 本发明涉及一种硅衬底，具体涉及一种电感器件及其制造方法，用于通过在硅衬底上设置沟槽来提高电感器的品质因数，并且通过用不掺杂杂质的多晶多晶硅填充沟槽内部 。 本发明提供一种电感器件及其制造方法，其可以通过在低电阻硅衬底上形成以特定图案设置的深沟槽并填充未掺杂杂质的多晶硅，并且通过 降低电感器和硅衬底之间的寄生电容。

公开(公告)号：US08754806B2

公开(公告)日：2014-06-17

申请号：US13316381

申请日：2011-12-09

申请人： Pil Jae Park ,  Seong Do Kim ,  Sung Chul Woo ,  Hyun Kyu Yu

发明人： Pil Jae Park ,  Seong Do Kim ,  Sung Chul Woo ,  Hyun Kyu Yu

IPC分类号： G01S7/285 ,  G01S7/00 ,  G01S13/10

CPC分类号： G01S7/292

摘要： A pulse radar receiver includes a power splitter configured to split a transmit (TX) trigger signal for generating a TX pulse, a phase-locked loop (PLL) configured to receive a division ratio and the TX trigger signal split by the power splitter, and generate a sampling frequency, and a sampler configured to sample a reflected wave received through an RX antenna, according to the sampling frequency generated by the PLL. Accordingly, it is possible to provide a high distance resolution by generating a sampling frequency with a difference from a TX pulse to sample a reflected wave received through an RX antenna. Thus, it is possible to overcome a limitation in the distance resolution due to the pulse width and to measure a minute movement at a short distance. Therefore, the pulse radar receiver is applicable to high range resolution radar applications such as a living body measuring radar.

摘要翻译： 脉冲雷达接收机包括：功率分配器，被配置为分离用于产生TX脉冲的发射（TX）触发信号;配置为接收分频比的锁相环（PLL）和由功率分配器分离的TX触发信号;以及 产生采样频率，并且采样器被配置为根据由PLL产生的采样频率对通过RX天线接收的反射波进行采样。 因此，通过产生与TX脉冲不同的采样频率来采样通过RX天线接收的反射波，可以提供高距离分辨率。 因此，可以克服由于脉冲宽度导致的距离分辨率的限制并且能够在短距离处测量微小的移动。 因此，脉冲雷达接收机适用于诸如生物体测量雷达的高范围分辨率雷达应用。