公开(公告)号：US5970325A

公开(公告)日：1999-10-19

申请号：US858974

申请日：1997-05-20

Applicant: Jin Jang ,  Keun-soo Lee ,  Jong-hyun Choi

Inventor： Jin Jang ,  Keun-soo Lee ,  Jong-hyun Choi

IPC: H01L21/205 ,  H01L21/336 ,  H01L29/786 ,  H01L29/78

CPC classification number: H01L29/66765 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/78669

Abstract: A thin-film switching device includes an active region including noncrystalline silicon, e.g., hydrogenated amorphous silicon, which includes chlorine distributed in a manner which produces a predetermined photoconductivity and a predetermined field-effect mobility in the active region. Preferably, the active region includes a plurality of hydrogenated amorphous silicon layers, at least one of which includes chlorine. In one embodiment, the plurality of hydrogenated amorphous silicon layers includes a hydrogenated amorphous silicon layer including between 0.1 ppm and 106 ppm chlorine. In another embodiment, the plurality of hydrogenated amorphous silicon layers includes a first hydrogenated amorphous silicon layer having a first chlorine concentration and a second hydrogenated amorphous silicon layer having a second chlorine concentration less than the first chlorine concentration. The first hydrogenated amorphous silicon layer includes 1 ppm to 105 ppm chlorine, and the second hydrogenated amorphous silicon layer includes less than 104 ppm chlorine. Related fabrication methods are also discussed.

Abstract translation: 薄膜开关器件包括包括非晶硅（例如氢化非晶硅）的有源区，其包括以有效区域中产生预定光电导率和预定场效应迁移率的方式分布的氯。 优选地，有源区包括多个氢化非晶硅层，其中至少一个包括氯。 在一个实施例中，多个氢化非晶硅层包括含0.1ppm至106ppm氯的氢化非晶硅层。 在另一实施例中，多个氢化非晶硅层包括具有第一氯浓度的第一氢化非晶硅层和具有小于第一氯浓度的第二氯浓度的第二氢化非晶硅层。 第一氢化非晶硅层包括1ppm至105ppm的氯，第二氢化非晶硅层包括小于104ppm的氯。 还讨论了相关的制造方法。

公开(公告)号：US5939149A

公开(公告)日：1999-08-17

申请号：US860770

申请日：1997-07-02

Applicant: Jin Jang ,  Kyu Chang Park

Inventor： Jin Jang ,  Kyu Chang Park

IPC: C01B31/06 ,  C23C14/06 ,  C23C14/58 ,  C23C16/26 ,  C23C16/27 ,  C23F4/00 ,  C30B25/00 ,  C30B29/04 ,  H01J9/02 ,  H01L21/205 ,  H01L21/302 ,  H01L21/3065 ,  B05D3/06 ,  H05H1/00

CPC classification number: H01J9/025 ,  C23C16/26 ,  C23C16/56

Abstract: The present invention relates to a method for forming substantially hydrogen free DLC layers, wherein DLC layer of thickness about 1 to 100 nanometers is deposited over a sample substrate or a field emitter array and subsequently exposed to etching plasma comprising fluorine gas, wherein during the latter step, hydrogen contained in the substrate is eliminated by chemical etching reaction with fluorine, wherein steps to form the hydrogen free DLC layer can be repeated to obtain a predetermined thickness of a DLC film.

Abstract translation: PCT No.PCT / KR96 / 00192 Sec。 371日期1997年7月2日 102（e）日期1997年7月2日PCT 1996年11月2日PCT公布。 公开号WO97 / 16580 日期1997年5月9日本发明涉及一种形成基本上无氢的DLC层的方法，其中厚度约1至100纳米的DLC层沉积在样品衬底或场致发射阵列上，随后暴露于蚀刻包含氟气的等离子体， 其中在后一步骤中，通过与氟的化学蚀刻反应来除去衬底中所含的氢，其中可以重复形成无氢DLC层的步骤以获得DLC膜的预定厚度。

公开(公告)号：US5783852A

公开(公告)日：1998-07-21

申请号：US697839

申请日：1996-08-30

Applicant: Jin Jang ,  Kyung-Ha Lee ,  You-Chan Chung

Inventor： Jin Jang ,  Kyung-Ha Lee ,  You-Chan Chung

IPC: H01L29/49 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L29/4908

Abstract: A thin film transistor includes an insulating substrate; a polysilicon pattern formed on the insulating substrate; a first nitride layer disposed on a channel portion of the polysilicon pattern; heavily doped semiconductor layer regions disposed in upper portions of the polysilicon pattern on sides of the first nitride layer pattern; an interlevel insulating layer disposed on the insulating substrate, the polysilicon pattern, the first nitride layer and the heavily doped semiconductor layer regions, the interlevel insulating layer having a contact hole to expose a portion of the heavily doped semiconductor layer; source and drain electrodes connected to the heavily doped semiconductor layer regions through the contact hole; and a gate electrode formed on the interlevel insulating layer disposed on the first nitride layer.

公开(公告)号：US5751017A

公开(公告)日：1998-05-12

申请号：US833205

申请日：1997-04-14

Applicant: Jin Jang ,  Hong Joo Lim ,  Bong Yool Ryu

Inventor： Jin Jang ,  Hong Joo Lim ,  Bong Yool Ryu

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/04

CPC classification number: H01L21/28158 ,  H01L29/4908 ,  H01L29/66757

Abstract: A thin film transistor and method includes a substrate and a first semiconductor layer formed on the substrate. A first insulating layer is formed on the first semiconductor layer, and a doped semiconductor layer is formed on an upper portion of the first semiconductor layer at first and second sides of the first insulating layer. A second insulating layer is formed on the first insulating layer and the doped semiconductor layer, the second insulating layer having contact holes. A gate electrode is formed on a portion of the second insulating layer, and source and drain electrodes are formed on portions of the second insulating layer, the source and drain electrodes contacting the doped semiconductor layer through the contact holes, respectively.

Abstract translation: 薄膜晶体管和方法包括基板和形成在基板上的第一半导体层。 在第一半导体层上形成第一绝缘层，并且在第一绝缘层的第一和第二侧在第一半导体层的上部形成掺杂半导体层。 在第一绝缘层和掺杂半导体层上形成第二绝缘层，第二绝缘层具有接触孔。 栅极电极形成在第二绝缘层的一部分上，源极和漏极分别形成在第二绝缘层的部分上，源极和漏极通过接触孔与掺杂半导体层接触。

公开(公告)号：US08052789B2

公开(公告)日：2011-11-08

申请号：US11594135

申请日：2006-11-08

Applicant: Jin Jang ,  Jae-Hwan Oh ,  Eun-Hyun Kim ,  Ki-Hyoung Kim

Inventor： Jin Jang ,  Jae-Hwan Oh ,  Eun-Hyun Kim ,  Ki-Hyoung Kim

IPC: C30B1/04

CPC classification number: B23K26/0738 ,  B23K26/082 ,  H01L21/0237 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02672 ,  H01L21/02678 ,  H01L21/02683 ,  H01L27/1281

Abstract: Disclosed are a polycrystalline silicon and a crystallization method thereof according to an exemplary embodiment of the present invention. The polycrystalline silicon comprises: an insulating substrate; and an optical portion formed on the insulating substrate for receiving a CW laser beam and varying the intensity of the beam in order of strength-weakness, strength-weakness, and strength-weakness on one dimension, so that an amorphous silicon thin film is crystallized. Therefore, the present invention can form a good polycrystalline silicon thin film by growing crystal grains with a constant direction and size, when an amorphous silicon thin film disposed on an insulating film such as a glass substrate is crystallized to a polycrystalline silicon thin film.

Abstract translation: 公开了根据本发明的示例性实施方案的多晶硅及其结晶方法。 多晶硅包括：绝缘基板; 以及形成在绝缘基板上的光学部分，用于接收CW激光束，并且在一个维度上按强度弱点，强度 - 弱度和强度 - 弱度的顺序改变光束的强度，使得非晶硅薄膜结晶 。 因此，当设置在诸如玻璃基板的绝缘膜上的非晶硅薄膜结晶到多晶硅薄膜时，本发明可以通过以恒定的方向和尺寸生长晶粒来形成良好的多晶硅薄膜。

公开(公告)号：US07884810B2

公开(公告)日：2011-02-08

申请号：US11396951

申请日：2006-04-03

Applicant: Jin Jang ,  Ji-Ho Hur ,  Se-Hwan Kim ,  Seung-Hyun Park

Inventor： Jin Jang ,  Ji-Ho Hur ,  Se-Hwan Kim ,  Seung-Hyun Park

IPC: G06F3/045

CPC classification number: G06K9/0002

Abstract: Unevenness detecting apparatus for compensating for threshold voltage and method thereof is provided with a plurality of scan lines and a plurality of data lines and a pixel circuit arranged in each point which the scan lines and the data lines are intersected. The unevenness detecting apparatus for compensating for the threshold voltage and method thereof may accurately sense a state of minute unevenness such as fingerprints by using an active element (e.g., TFT) as an element of which pixel circuit is composed.

Abstract translation: 用于补偿阈值电压的不均匀性检测装置及其方法具有多条扫描线和多条数据线以及排列在扫描线和数据线相交的各点的像素电路。 用于补偿阈值电压的不均匀性检测装置及其方法可以通过使用有源元件（例如TFT）作为构成像素电路的元件来精确地感测诸如指纹的微小不均匀的状态。

公开(公告)号：US20100327354A1

公开(公告)日：2010-12-30

申请号：US12865006

申请日：2009-01-27

Applicant: Jin Jang ,  Carlo Anthony Kosik Williams ,  ChuanChe Wang

Inventor： Jin Jang ,  Carlo Anthony Kosik Williams ,  ChuanChe Wang

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/78621 ,  H01L27/3262

Abstract: Methods and apparatus for producing a thin film transistor (TFT) result in: a glass or glass ceramic substrate; a single crystal semiconductor layer; a source structure disposed on the single crystal semiconductor layer; a drain structure disposed on the single crystal semiconductor layer; and a gate structure located with respect to the drain structure defining a lightly doped drain region therein, wherein a lateral length of the lightly doped drain region is such that the TFT exhibits a relatively low carrier mobility and moderate sub-threshold slope suitable for OLED display applications.

Abstract translation: 用于制造薄膜晶体管（TFT）的方法和设备导致：玻璃或玻璃陶瓷衬底; 单晶半导体层; 设置在单晶半导体层上的源极结构; 设置在单晶半导体层上的漏极结构; 以及相对于在其中限定轻掺杂漏极区的漏极结构定位的栅结构，其中轻掺杂漏极区的横向长度使得TFT表现出相对较低的载流子迁移率和适合于OLED显示的适度亚阈值斜率 应用程序。

公开(公告)号：US20100201251A1

公开(公告)日：2010-08-12

申请号：US12295943

申请日：2007-04-04

Applicant: Kyu Chang Park ,  Jin Jang ,  Je Hwang Ryu

Inventor： Kyu Chang Park ,  Jin Jang ,  Je Hwang Ryu

IPC: H01J1/62 ,  H01J9/20

CPC classification number: H01J9/025 ,  B82Y10/00 ,  H01J31/127 ,  H01J2201/30469

Abstract: The present invention relates to a field emission display and a manufacturing method of the same having selective positioning of electron field emitters. More specifically, the present invention provides a field emission display and a manufacturing method of the same having selective positioning of electron field emitters which can prevent a cross-talk that is a mutual interference phenomenon between pixels and improve uniformity of pixels based on uniform electron emission by deciding positions of carbon nano-tubes which are sources of electron emission and growing carbon nano-tubes before the structure of electrodes is formed, and forming spacers directly on electrodes such that the spacers divide carbon nano-tubes formed uniformly and selectively into pixel units.

Abstract translation: 本发明涉及具有电子场发射器的选择性定位的场致发射显示器及其制造方法。 更具体地说，本发明提供了具有选择性定位电子场发射体的场致发射显示器及其制造方法，其可以防止作为像素之间的相互干扰现象的串扰，并且基于均匀的电子发射来改善像素的均匀性 通过在形成电极结构之前确定作为电子发射源和生长碳纳米管的碳纳米管的位置，并且直接在电极上形成间隔物，使得间隔物将均匀且有选择地形成的碳纳米管分成像素单元 。

公开(公告)号：US07442588B2

公开(公告)日：2008-10-28

申请号：US11830010

申请日：2007-07-30

Applicant: Jin Jang ,  Se-Hwan Kim ,  Youn-Duck Nam ,  Eung-Bum Kim ,  Ji-Ho Hur

Inventor： Jin Jang ,  Se-Hwan Kim ,  Youn-Duck Nam ,  Eung-Bum Kim ,  Ji-Ho Hur

IPC: H01L21/00

CPC classification number: H01L29/7869

Abstract: Disclosed is a method for fabricating a thin film transistor. Specifically, the method uses local oxidation wherein a portion of a transparent metal oxide layer is locally oxidized to be converted into a semiconductor layer so that the oxidized portion of the transparent metal oxide layer can be used as a channel region and the unoxidized portions of the transparent metal oxide layer can be used as source and drain electrodes.The method comprises the steps of forming a gate electrode on a substrate and forming a gate insulating layer thereon, forming a transparent metal oxide layer on the gate insulating layer, forming an oxidation barrier layer on the transparent metal oxide layer in such a manner that a portion of the transparent metal oxide layer positioned over the gate electrode is exposed, and locally oxidizing only the exposed portion of the transparent metal oxide layer to convert the exposed portion into a semiconductor layer.

Abstract translation: 公开了一种制造薄膜晶体管的方法。 具体地，该方法使用局部氧化，其中透明金属氧化物层的一部分被局部氧化以转化为半导体层，使得透明金属氧化物层的氧化部分可以用作沟道区域，并且所述非氧化部分 透明金属氧化物层可以用作源极和漏极。 该方法包括以下步骤：在衬底上形成栅电极并在其上形成栅极绝缘层，在栅绝缘层上形成透明金属氧化物层，在透明金属氧化物层上形成氧化阻挡层， 露出位于栅电极上方的透明金属氧化物层的部分，仅局部氧化透明金属氧化物层的露出部分，将露出部分转换为半导体层。

公开(公告)号：US07339188B1

公开(公告)日：2008-03-04

申请号：US09497508

申请日：2000-02-04

Applicant: Jin Jang ,  Seong-Jin Park

Inventor： Jin Jang ,  Seong-Jin Park

IPC: H01L29/04

CPC classification number: H01L21/02422 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02672 ,  H01L27/1277 ,  H01L27/1285 ,  H01L27/1296

Abstract: The present invention is related to a polycrystalline silicon film containing Ni which is formed by crystallizing an amorphous silicon layer containing nickel. The present invention includes a polycrystalline silicon film wherein the polycrystalline film contains Ni atoms of which density ranges from 2×1017 to 5×1019 atoms/cm3 on average and comprises a plurality of needle-shaped silicon crystallites. In another aspect, the present invention includes a polycrystalline silicon film wherein the polycrystalline film contains Ni atoms of which density ranges from 2×1017 to 5×1019 atoms/cm3, comprises a plurality of needle-shaped silicon crystallites and is formed on an insulating substrate. Such a polysilicon film according to the present invention avoids metal contamination usually generated in a conventional method of metal induced crystallization.

Abstract translation: 本发明涉及通过使包含镍的非晶硅层结晶而形成的含有Ni的多晶硅膜。 本发明包括多晶硅膜，其中多晶膜含有浓度范围为2×10 17至5×10 19原子/ cm 3的Ni原子。 并且包括多个针状硅微晶。 另一方面，本发明包括多晶硅膜，其中多晶膜含有密度为2×10 17至5×10 19原子/ cm 3的Ni原子 包括多个针状硅微晶，并形成在绝缘基板上。 根据本发明的这种多晶硅膜避免了通常以常规的金属诱导结晶方法产生的金属污染。