公开(公告)号：US5907762A

公开(公告)日：1999-05-25

申请号：US984789

申请日：1997-12-04

申请人： David R. Evans ,  Sheng Teng Hsu ,  Jong Jan Lee

发明人： David R. Evans ,  Sheng Teng Hsu ,  Jong Jan Lee

IPC分类号： H01L21/318 ,  H01L21/304 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L29/78 ,  H01L21/00

CPC分类号： H01L29/66477 ,  H01L29/78391

摘要： A method of constructing a single-transistor ferroelectric memory (FEM) cell includes: preparing a silicon substrate for construction of a FEM gate unit; forming gate, source and drain regions on the silicon substrate; forming a nitride layer over the structure to a predetermined thickness equal to a specified thickness for a bottom electrode of the FEM gate unit; forming a first insulating layer over the structure; chemically-mechanically polishing the first insulating layer such that the top surface thereof is even with the top of the nitride layer; forming the bottom electrode for the FEM cell; and chemically-mechanically polishing the bottom electrode such that the top surface thereof is even with the top surface of the first insulating layer. Additional layers are formed and polished, depending on the specific final configuration of the FEM cell.

摘要翻译： 构成单晶体管铁电存储器（FEM）单元的方法包括：制备用于构造有限元栅极单元的硅衬底; 在硅衬底上形成栅极，源极和漏极区域; 在所述结构上形成等于所述FEM栅极单元的底部电极的指定厚度的预定厚度的氮化物层; 在所述结构上形成第一绝缘层; 化学机械抛光第一绝缘层，使得其顶表面与氮化物层的顶部均匀; 形成有限元电池的底电极; 并对底部电极进行化学机械抛光，使得其顶表面与第一绝缘层的顶表面均匀。 根据FEM单元的具体最终配置，形成和抛光附加层。

公开(公告)号：US4866728A

公开(公告)日：1989-09-12

申请号：US166381

申请日：1988-02-04

申请人： David R. Evans ,  John E. Harry

发明人： David R. Evans ,  John E. Harry

IPC分类号： H01S3/038

CPC分类号： H01S3/038 ,  H01S3/0381

摘要： A gas laser includes a laser cavity, mirror means defining an optical path in the cavity, electrodes defining an electric discharge path in the cavity, the electrodes including at least one anode member having a passage therethrough which at one end opens into the cavity, and gas supply means for injecting gas into the cavity through the passage, wherein the wall of the passage at said one end and the exterior of the anode member around the end of said passage is electrically insulated and an electrically conducting anode surface defining the root of the discharge is provided inwardly of the perimeter of the open end of the passage.

摘要翻译： 气体激光器包括激光腔，在空腔中限定光路的反射镜装置，限定空腔中的放电路径的电极，所述电极包括至少一个具有穿过其中的通道的阳极部件，其一端通向腔体，以及 用于通过通道将气体注入空腔的气体供应装置，其中围绕所述通道端部的所述一端的所述通道的壁和所述阳极构件的外部是电绝缘的，并且限定所述通道的根部的导电阳极表面 在通道的开口端的周边的内侧设置放电。

公开(公告)号：US08810897B2

公开(公告)日：2014-08-19

申请号：US13434548

申请日：2012-03-29

申请人： Akinori Hashimura ,  Liang Tang ,  David R. Evans

发明人： Akinori Hashimura ,  Liang Tang ,  David R. Evans

IPC分类号： G02B26/00 ,  G02F1/167

CPC分类号： G02F1/167 ,  B05D5/12 ,  G02F1/1334 ,  G02F1/13439 ,  G02F1/23 ,  G02F2202/36 ,  G02F2203/10 ,  G02F2203/34

摘要： A method is provided for improving metallic nanostructure stability. The method provides a substrate, and using a physical vapor deposition (PVD) process for example, deposits metallic nanostructures having a first diameter overlying the substrate. Some examples of metallic nanostructures include Ag, Au, and Al. The metallic nanostructures are annealed in an atmosphere including an inert gas and H2. The annealing temperature is less than the melting temperature the metal material in bulk form. In response to the annealing, stabilized metallic nanostructures are formed. If the stabilized metallic nanostructures are exposed to an ambient air environment the stabilized metallic nanostructure maintain the first diameter. Typically, the metallic nanostructures are initially formed having a rectangular shape with corners. After annealing, the stabilized metallic nanostructures have a dome shape.

摘要翻译： 提供了一种提高金属纳米结构稳定性的方法。 该方法提供基底，并且例如使用物理气相沉积（PVD）工艺沉积具有覆盖在基底上的第一直径的金属纳米结构。 金属纳米结构的一些实例包括Ag，Au和Al。 金属纳米结构在包括惰性气体和H 2的气氛中退火。 退火温度小于块状形式的金属材料的熔融温度。 响应于退火，形成稳定的金属纳米结构。 如果稳定的金属纳米结构暴露于环境空气环境，则稳定的金属纳米结构保持第一直径。 通常，金属纳米结构最初形成为具有角部的矩形形状。 退火后，稳定的金属纳米结构具有圆顶形状。

公开(公告)号：US20130077036A1

公开(公告)日：2013-03-28

申请号：US13434548

申请日：2012-03-29

申请人： Akinori Hashimura ,  Liang Tang ,  David R. Evans

发明人： Akinori Hashimura ,  Liang Tang ,  David R. Evans

IPC分类号： B05D5/12 ,  G02F1/1343

CPC分类号： G02F1/167 ,  B05D5/12 ,  G02F1/1334 ,  G02F1/13439 ,  G02F1/23 ,  G02F2202/36 ,  G02F2203/10 ,  G02F2203/34

摘要： A method is provided for improving metallic nanostructure stability. The method provides a substrate, and using a physical vapor deposition (PVD) process for example, deposits metallic nanostructures having a first diameter overlying the substrate. Some examples of metallic nanostructures include Ag, Au, and Al. The metallic nanostructures are annealed in an atmosphere including an inert gas and H2. The annealing temperature is less than the melting temperature the metal material in bulk form. In response to the annealing, stabilized metallic nanostructures are formed. If the stabilized metallic nanostructures are exposed to an ambient air environment the stabilized metallic nanostructure maintain the first diameter. Typically, the metallic nanostructures are initially formed having a rectangular shape with corners. After annealing, the stabilized metallic nanostructures have a dome shape.

摘要翻译： 提供了一种提高金属纳米结构稳定性的方法。 该方法提供基底，并且例如使用物理气相沉积（PVD）工艺沉积具有覆盖在基底上的第一直径的金属纳米结构。 金属纳米结构的一些实例包括Ag，Au和Al。 金属纳米结构在包括惰性气体和H 2的气氛中退火。 退火温度小于块状形式的金属材料的熔融温度。 响应于退火，形成稳定的金属纳米结构。 如果稳定的金属纳米结构暴露于环境空气环境，则稳定的金属纳米结构保持第一直径。 通常，金属纳米结构最初形成为具有角部的矩形形状。 退火后，稳定的金属纳米结构具有圆顶形状。

公开(公告)号：US20090032817A1

公开(公告)日：2009-02-05

申请号：US12234663

申请日：2008-09-21

申请人： Tingkai Li ,  Sheng Teng Hsu ,  David R. Evans

发明人： Tingkai Li ,  Sheng Teng Hsu ,  David R. Evans

IPC分类号： H01L29/04 ,  H01L21/329

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/31 ,  H01L27/2409 ,  H01L29/66143 ,  H01L29/872 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.

摘要翻译： 提供了用于从硅（Si）半导体形成金属/半导体/金属（MSM）背对背肖特基二极管的方法。 该方法在底电极和顶电极之间沉积Si半导体层，并形成具有阈值电压，击穿电压和开/关电流比的MSM二极管。 响应于控制Si半导体层厚度，该方法能够修改MSM二极管的阈值电压，击穿电压和导通/截止电流比。 通常，响应于Si厚度的增加，阈值和击穿电压都增加。 关于开/关电流比，存在最佳厚度。 该方法能够使用化学气相沉积（CVD）或DC溅射形成非晶Si（a-Si）和多晶硅（polySi）半导体层。 Si半导体可以掺杂有V族施主材料，其降低阈值电压并增加击穿电压。

公开(公告)号：US07364665B2

公开(公告)日：2008-04-29

申请号：US10970885

申请日：2004-10-21

申请人： Tingkai Li ,  Bruce D. Ulrich ,  David R. Evans ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Bruce D. Ulrich ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00

CPC分类号： H01L29/6684 ,  C23F4/00 ,  H01L21/28291 ,  H01L21/31116 ,  H01L21/32136

摘要： A method of selectively etching a three-layer structure consisting of SiO2, In2O3, and titanium, includes etching the SiO2, stopping at the titanium layer, using C3F8 in a range of between about 10 sccm to 30 sccm; argon in a range of between about 20 sccm to 40 sccm, using an RF source in a range of between about 1000 watts to 3000 watts and an RF bias in a range of between about 400 watts to 800 watts at a pressure in a range of between about 2 mtorr to 6 mtorr; and etching the titanium, stopping at the In2O3 layer, using BCl in a range of between about 10 sccm to 50 sccm; chlorine in a range of between about 40 sccm to 80 sccm, a Tcp in a range of between about 200 watts to 500 watts at an RF bias in a range of between about 100 watts to 200 watts at a pressure in a range of between about 4 mtorr to 8 mtorr.

摘要翻译： 选择性地蚀刻由SiO 2，In 2 O 3 N 3和Ti构成的三层结构的方法包括蚀刻SiO _{2 ，在钛层上停止，使用C 3 3 F 8 N在约10sccm至30sccm之间; 在约20sccm至40sccm的范围内的氩气，使用在约1000瓦特至3000瓦特之间的范围内的RF源和在约400瓦特至800瓦特范围内的RF偏压， 约2mtorr至6mtorr; 并且使用在约10sccm至50sccm之间的范围内的BCl蚀刻钛，停止在In 2 N 3 O 3层处; 在约40sccm至80sccm的范围内的氯，在约200瓦特至200瓦特之间的RF偏压下在约200瓦特至500瓦特之间的范围内的T cp < 在约4mtorr至8mtorr的范围内的压力。}

公开(公告)号：US07361574B1

公开(公告)日：2008-04-22

申请号：US11601173

申请日：2006-11-17

申请人： Jer-Shen Maa ,  David R. Evans ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

发明人： Jer-Shen Maa ,  David R. Evans ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

IPC分类号： H01L21/30 ,  H01L21/461

CPC分类号： H01L21/76251 ,  H01L21/84 ,  Y10S438/926 ,  Y10S438/933

摘要： A method is provided for transferring a single-crystal silicon (Si) film to a glass substrate. The method deposits a germanium (Ge)-containing material overlying a Si wafer, forming a sacrificial Ge-containing film. A single-crystal Si film is formed overlying the sacrificial Ge-containing film. The Si film surface is bonded to a transparent substrate, forming a bonded substrate. The bonded substrate is immersed in a Ge etching solution to remove the sacrificial Ge-containing film, which separates the transparent substrate from the Si wafer. The result is a transparent substrate with an overlying single crystal Si film. Optionally, channels can be formed to distribute the Ge etching solution, and promote the removal of the Ge-containing film.

摘要翻译： 提供了将单晶硅（Si）膜转印到玻璃基板上的方法。 该方法沉积覆盖Si晶片的含锗（Ge）的材料，形成牺牲含Ge膜。 形成覆盖牺牲的含Ge膜的单晶Si膜。 将Si膜表面粘合到透明基板上，形成键合衬底。 将键合衬底浸入Ge蚀刻溶液中以除去将透明衬底与Si晶片分离的牺牲Ge含量膜。 结果是具有上覆单晶Si膜的透明衬底。 可选地，可以形成通道以分布Ge蚀刻溶液，并促进除去含Ge膜。

公开(公告)号：US07241670B2

公开(公告)日：2007-07-10

申请号：US10936400

申请日：2004-09-07

申请人： Douglas J. Tweet ,  David R. Evans ,  Sheng Teng Hsu ,  Jer-Shen Maa

发明人： Douglas J. Tweet ,  David R. Evans ,  Sheng Teng Hsu ,  Jer-Shen Maa

IPC分类号： H01L21/26 ,  H01L21/42

CPC分类号： H01L21/02694 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L29/1054 ,  Y10S438/933

摘要： A method of forming a relaxed SiGe layer having a high germanium content in a semiconductor device includes preparing a silicon substrate; depositing a strained SiGe layer; implanting ions into the strained SiGe layer, wherein the ions include silicon ions and ions selected from the group of ions consisting of boron and helium, and which further includes implanting H+ ions; annealing to relax the strained SiGe layer, thereby forming a first relaxed SiGe layer; and completing the semiconductor device.

摘要翻译： 在半导体器件中形成具有高锗含量的弛豫SiGe层的方法包括制备硅衬底; 沉积应变SiGe层; 将离子注入到应变SiGe层中，其中离子包括选自由硼和氦构成的离子组的硅离子和离子，并且还包括注入H +离子; 退火以使应变SiGe层松弛，从而形成第一弛豫SiGe层; 并完成半导体器件。

公开(公告)号：US07192866B2

公开(公告)日：2007-03-20

申请号：US10326712

申请日：2002-12-19

申请人： Wei Pan ,  David R. Evans ,  Sheng Teng Hsu

发明人： Wei Pan ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/28556 ,  H01L2221/1078

摘要： An alternating source MOCVD process is provided for depositing tungsten nitride thin films for use as barrier layers for copper interconnects. Alternating the tungsten precursor produces fine crystal grain films, or possibly amorphous films. The nitrogen source may also be alternated to form WN/W alternating layer films, as tungsten is deposited during periods where the nitrogen source is removed.

摘要翻译： 提供了用于沉积用作铜互连的阻挡层的氮化钨薄膜的交替源MOCVD工艺。 交替钨前体产生细晶粒膜或可能的非晶膜。 氮源也可以交替形成WN / W交替层膜，因为在氮源被去除的时期期间钨被沉积。

公开(公告)号：US06939724B2

公开(公告)日：2005-09-06

申请号：US10640770

申请日：2003-08-13

申请人： Wei-Wei Zhuang ,  Tingkai Li ,  David R. Evans ,  Sheng Teng Hsu ,  Wei Pan

发明人： Wei-Wei Zhuang ,  Tingkai Li ,  David R. Evans ,  Sheng Teng Hsu ,  Wei Pan

IPC分类号： H01L27/04 ,  H01L21/20 ,  H01L21/822 ,  H01L45/00 ,  H01L21/00

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608

摘要： A method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer includes depositing, by MOCVD, a seed layer of PCMO, in highly crystalline form, thin film, having a thickness of between about 50 Å to 300 Å, depositing a second PCMO thin film layer on the seed layer, by spin coating, having a thickness of between about 500 Å to 3000 Å, to form a combined PCMO layer; increasing the resistance of the combined PCMO film in a semiconductor device by applying a negative electric pulse of between about −4V to −5V, having a pulse width of between about 75 nsec to 1 μsec; and decreasing the resistance of the combined PCMO layer in a semiconductor device by applying a positive electric pulse of between about +2.5V to +4V, having a pulse width greater than 2.0 μsec.