公开(公告)号：US5807791A

公开(公告)日：1998-09-15

申请号：US785032

申请日：1997-01-02

申请人： Claude Louis Bertin ,  Erik Leigh Hedberg ,  James Marc Leas ,  Steven Howard Voldman

发明人： Claude Louis Bertin ,  Erik Leigh Hedberg ,  James Marc Leas ,  Steven Howard Voldman

IPC分类号： H01L23/528 ,  H01L23/60 ,  H01L25/065 ,  H01L27/02 ,  G11C5/06

CPC分类号： H01L23/5286 ,  H01L23/60 ,  H01L25/0657 ,  H01L27/0251 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2924/0002 ,  H01L2924/3011

摘要： Multichip semiconductor structures with consolidated circuitry are disclosed, along with programmable electrostatic discharge (ESD) protection circuits for chip input/output (I/O) nodes. The multichip structures include a first semiconductor chip having a first circuit at least partially providing a first predetermined circuit function, and a second semiconductor chip electrically and mechanically coupled to the first semiconductor chip. The second semiconductor device chip has a second circuit that at least partially provides a circuit function to the first circuit of the first semiconductor chip. In one embodiment, the first semiconductor chip comprises a memory array chip, while the second semiconductor chip comprises a logic chip wherein at least some peripheral circuitry necessary for accessing the memory array of the memory array chip resides within the logic chip. This allows the removal of redundant circuitry from identical chips of a multichip structure. Also disclosed is removing, adding or balancing ESD circuit loading on input/output nodes of a multichip stack. Various techniques are presented for selective removal of ESD circuitry from commonly connected I/O nodes. Any circuitry interfacing with an external device may be rebalanced at the multichip level using this concept.

摘要翻译： 公开了具有整合电路的多芯片半导体结构，以及用于芯片输入/输出（I / O）节点的可编程静电放电（ESD）保护电路。 多芯片结构包括具有至少部分地提供第一预定电路功能的第一电路的第一半导体芯片，以及电和机械耦合到第一半导体芯片的第二半导体芯片。 第二半导体器件芯片具有至少部分地向第一半导体芯片的第一电路提供电路功能的第二电路。 在一个实施例中，第一半导体芯片包括存储器阵列芯片，而第二半导体芯片包括逻辑芯片，其中访问存储器阵列芯片的存储器阵列所需的至少一些外围电路驻留在逻辑芯片内。 这允许从多芯片结构的相同芯片去除冗余电路。 还公开了在多芯片堆叠的输入/输出节点上移除，添加或平衡ESD电路负载。 提出了各种技术，用于从共同连接的I / O节点选择性地去除ESD电路。 与外部设备接口的任何电路可以使用这个概念在多芯片级别重新平衡。

公开(公告)号：US5786237A

公开(公告)日：1998-07-28

申请号：US515611

申请日：1995-08-16

申请人： Martha Ashley Clark Cockerill ,  John George Maltabes ,  Loretta Jean O'Connor ,  Steven Howard Voldman

发明人： Martha Ashley Clark Cockerill ,  John George Maltabes ,  Loretta Jean O'Connor ,  Steven Howard Voldman

IPC分类号： H01L25/00 ,  H01L21/66 ,  H01L21/98 ,  H01L25/065 ,  H01L21/60 ,  H01L21/70

CPC分类号： H01L25/50 ,  H01L22/20 ,  H01L25/0657 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2924/0002

摘要： A fabrication method for manufacturing a monolithic electronic module comprising a plurality of stacked planar extending arrays of integrated circuit chips. The fabrication method includes dicing a wafer of integrated circuit chips into a plurality of arrays of integrated circuit chips. The arrays of integrated circuit chips are then stacked to form an electronic module. A metallization pattern may be deposited on a substantially planar surface of the electronic module, and used to interconnect the various arrays of integrated circuit chips contained therein. Specific details of the fabrication method and resultant multi-chip package are set forth.

摘要翻译： 一种用于制造单片电子模块的制造方法，包括多个堆叠的平面扩展阵列的集成电路芯片。 该制造方法包括将集成电路芯片的晶片切割成多个集成电路芯片阵列。 然后将集成电路芯片的阵列堆叠以形成电子模块。 金属化图案可以沉积在电子模块的基本平坦的表面上，并且用于互连其中包含的各种集成电路芯片阵列。 阐述制造方法和结果多芯片封装的具体细节。

公开(公告)号：US5731945A

公开(公告)日：1998-03-24

申请号：US778399

申请日：1997-01-02

申请人： Claude Louis Bertin ,  Erik Leight Hedberg ,  James Maro Leas ,  Steven Howard Voldman

发明人： Claude Louis Bertin ,  Erik Leight Hedberg ,  James Maro Leas ,  Steven Howard Voldman

IPC分类号： H01L23/528 ,  H01L23/60 ,  H01L25/065 ,  H01L27/02 ,  H02H3/22

CPC分类号： H01L23/5286 ,  H01L23/60 ,  H01L25/0657 ,  H01L27/0251 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2924/0002 ,  H01L2924/3011

摘要： Multichip semiconductor structures with consolidated circuitry are disclosed, along with programmable electrostatic discharge (ESD) protection circuits for chip input/output (I/O) nodes. The multichip structures include a first semiconductor chip having a first circuit at least partially providing a first predetermined circuit function, and a second semiconductor chip electrically and mechanically coupled to the first semiconductor chip. The second semiconductor device chip has a second circuit that at least partially provides a circuit function to the first circuit of the first semiconductor chip. In one embodiment, the first semiconductor chip comprises a memory array chip, while the second semiconductor chip comprises a logic chip wherein at least some peripheral circuitry necessary for accessing the memory array of the memory array chip resides within the logic chip. This allows the removal of redundant circuitry from identical chips of a multichip structure. Also disclosed is removing, adding or balancing ESD circuit loading on input/output nodes of a multichip stack. Various techniques are presented for selective removal of ESD circuitry from commonly connected I/O nodes. Any circuitry interfacing with an external device may be rebalanced at the multichip level using this concept.

摘要翻译： 公开了具有整合电路的多芯片半导体结构，以及用于芯片输入/输出（I / O）节点的可编程静电放电（ESD）保护电路。 多芯片结构包括具有至少部分地提供第一预定电路功能的第一电路的第一半导体芯片，以及电和机械耦合到第一半导体芯片的第二半导体芯片。 第二半导体器件芯片具有至少部分地向第一半导体芯片的第一电路提供电路功能的第二电路。 在一个实施例中，第一半导体芯片包括存储器阵列芯片，而第二半导体芯片包括逻辑芯片，其中访问存储器阵列芯片的存储器阵列所需的至少一些外围电路驻留在逻辑芯片内。 这允许从多芯片结构的相同芯片去除冗余电路。 还公开了在多芯片堆叠的输入/输出节点上移除，添加或平衡ESD电路负载。 提出了各种技术，用于从共同连接的I / O节点选择性地去除ESD电路。 与外部设备接口的任何电路可以使用这个概念在多芯片级别重新平衡。

公开(公告)号：US5710682A

公开(公告)日：1998-01-20

申请号：US799259

申请日：1997-02-13

申请人： Satya P. Arya ,  Timothy Scott Hughbanks ,  Steven Howard Voldman ,  Albert John Wallash

发明人： Satya P. Arya ,  Timothy Scott Hughbanks ,  Steven Howard Voldman ,  Albert John Wallash

IPC分类号： G11B5/40 ,  G11B5/48 ,  G11B5/60 ,  G11B19/02 ,  G11B21/16

CPC分类号： G11B5/4853 ,  G11B5/40 ,  G11B5/4886 ,  G11B19/02 ,  G11B5/6011

摘要： An MR head receives ESD protection from a mechanism that automatically and releasably shorts the MR head whenever a suspension assembly on which the head is mounted is not installed in an HDA. The suspension assembly includes a flexure underlying a load beam, which is connected to an actuator arm. The MR head is mounted to a distal end of the flexure, leads from components of the MR head being brought out in the form of MR wire leads running along the load beam and the support arm to a nearby terminal connecting side tab. The conductors are separated and exposed at a designated point along the flexure to provide a contact region. A shorting bar, which comprises an electrically conductive member attached to the actuator arm, automatically connects the MR wire leads at the contact region when absence of support for the MR head permits the load beam to bend sufficiently toward the shorting bar. Thus, when the assembly is removed from installation in an HDA, the flexure is permitted to move toward the shorting bar, bringing the contact region and the shorting bar in electrical contact to short the MR wired leads and thereby disable the MR sensor. When the assembly is installed in an HDA, the MR head is supported by an air bearing or the disk itself, depending upon whether the disk is rotating or stopped, respectively. In either case, the load beam is not permitted to droop and the shorting bar cannot contact the conductors, thus activating the MR sensor. Temporary ESD protection mechanisms are also provided, these being removable prior to operation of the HDA by breaking and removing various temporary shorting mechanisms.

摘要翻译： 每当安装有头部的悬挂组件未安装在HDA中时，MR磁头可以从机构自动和可释放地短路MR头部获得ESD保护。 悬架组件包括连接到致动器臂的负载梁下方的挠曲件。 MR头被安装到挠曲件的远端，从MR头的部件引出的MR导线沿着负载梁和支撑臂延伸到附近的端子连接侧突出部的形式被引出。 导体沿着挠曲件在指定点处分离并暴露以提供接触区域。 包括连接到致动器臂的导电构件的短路棒在没有用于MR头的支撑的情况下在接触区域处自动连接MR线引线，允许负载梁朝向短路棒充分弯曲。 因此，当组件从HDA中的安装中移除时，允许挠曲件朝向短路棒移动，使接触区域和短路棒电接触以缩短MR有线引线，从而禁用MR传感器。 当组件安装在HDA中时，MR磁头由空气轴承或磁盘本身支撑，这取决于磁盘是分别旋转还是停止。 在任一情况下，负载梁不允许下垂，并且短路棒不能接触导体，从而启动MR传感器。 还提供了临时ESD保护机制，它们在HDA操作之前可以通过断开和移除各种临时短路机构来拆卸。

公开(公告)号：US5656553A

公开(公告)日：1997-08-12

申请号：US655529

申请日：1996-05-30

申请人： James Marc Leas ,  Steven Howard Voldman

发明人： James Marc Leas ,  Steven Howard Voldman

IPC分类号： H01L25/00 ,  H01L21/66 ,  H01L21/98 ,  H01L25/065 ,  H01L21/302

CPC分类号： H01L25/50 ,  H01L22/20 ,  H01L25/0657 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2924/0002

摘要： A fabrication method and resultant monolithic electronic module comprising a plurality of stacked planar extending arrays of integrated circuit chips. The fabrication method includes dicing a wafer of integrated circuit chips into a plurality of arrays of integrated circuit chips. The arrays of integrated circuit chips are then stacked to form an electronic module. A metallization pattern may be deposited on a substantially planar surface of the electronic module, and used to interconnect the various arrays of integrated circuit chips contained therein. Specific details of the fabrication method and resultant multi-chip package are set forth.

摘要翻译： 一种制造方法和合成的单片电子模块，其包括多个堆叠的平面扩展阵列的集成电路芯片。 该制造方法包括将集成电路芯片的晶片切割成多个集成电路芯片阵列。 然后将集成电路芯片的阵列堆叠以形成电子模块。 金属化图案可以沉积在电子模块的基本平坦的表面上，并且用于互连其中包含的各种集成电路芯片阵列。 阐述制造方法和结果多芯片封装的具体细节。

公开(公告)号：US08859337B2

公开(公告)日：2014-10-14

申请号：US12966728

申请日：2010-12-13

申请人： Stephen J Gaul ,  Steven Howard Voldman ,  Jean-Michel Tschann

发明人： Stephen J Gaul ,  Steven Howard Voldman ,  Jean-Michel Tschann

IPC分类号： H01L21/00 ,  H01L29/861 ,  H01L23/367 ,  H01L23/60 ,  H01L23/373 ,  H01L29/737 ,  H01L29/73 ,  H01L29/06

CPC分类号： H01L29/861 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3732 ,  H01L23/60 ,  H01L29/0653 ,  H01L29/73 ,  H01L29/737 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

摘要： Embodiments described herein provide a chip, comprising a first device on a substrate and a second device on the substrate. The chip further comprises a heat distribution structure in thermal proximity to the first device and the second device, wherein the heat distribution structure is thermally isolated and reduces a thermal gradient between the first device and the second device.

摘要翻译： 本文描述的实施例提供一种芯片，其包括在基板上的第一器件和衬底上的第二器件。 芯片还包括热接近第一器件和第二器件的热分布结构，其中热分布结构被热隔离并且减小第一器件和第二器件之间的热梯度。

公开(公告)号：US08143671B2

公开(公告)日：2012-03-27

申请号：US12640192

申请日：2009-12-17

申请人： Steven Howard Voldman

发明人： Steven Howard Voldman

IPC分类号： H01L21/8238

CPC分类号： H01L29/0847 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/7834 ,  H01L29/7835

摘要： A semiconductor structure and associated method of formation. The semiconductor structure includes a semiconductor substrate, a first doped transistor region of a first transistor and a first doped Source/Drain portion of a second transistor on the semiconductor substrate, a second gate dielectric layer and a second gate electrode region of the second transistor on the semiconductor substrate, a first gate dielectric layer and a first gate electrode region of the first transistor on the semiconductor substrate, and a second doped transistor region of the first transistor and a second doped Source/Drain portion of the second transistor on the semiconductor substrate. The first and second gate dielectric layers are sandwiched between and electrically insulate the semiconductor substrate from the first and second gate electrode regions, respectively. The first and second gate electrode regions are totally above and totally below, respectively, the top substrate surface.

摘要翻译： 半导体结构及其相关联的形成方法。 半导体结构包括半导体衬底，第一晶体管的第一掺杂晶体管区域和半导体衬底上的第二晶体管的第一掺杂源极/漏极部分，第二栅极电介质层和第二晶体管的第二栅极电极区域 所述半导体衬底，所述半导体衬底上的所述第一晶体管的第一栅极介电层和第一栅极电极区域以及所述第一晶体管的第二掺杂晶体管区域和所述半导体衬底上的所述第二晶体管的第二掺杂源极/漏极部分 。 第一和第二栅极电介质层分别夹在半导体衬底和第一和第二栅极电极区域之间并将其电绝缘。 第一和第二栅极电极区域分别在顶部衬底表面上方并且完全在下方。

公开(公告)号：US08088656B2

公开(公告)日：2012-01-03

申请号：US12541484

申请日：2009-08-14

申请人： Steven Howard Voldman

发明人： Steven Howard Voldman

IPC分类号： H01L21/8238 ,  H01L21/328

CPC分类号： H01L21/823892 ,  H01L21/823814 ,  H01L27/0266 ,  H01L29/66659 ,  H01L29/7835

摘要： A method, including; simultaneously forming a first doped region of an electrostatic discharge protection device and a second doped region of a high-power device by performing a first ion implantation into a semiconductor substrate; and simultaneously forming a third doped region of the electrostatic discharge protection device and a fourth doped region of a first low power device by performing a second ion implantation into the semiconductor substrate, the first ion implantation different from the second ion implantation, the electrostatic discharge device being a different device type from the high-power device and the electrostatic discharge device having a different structure from the high-power device.

摘要翻译： 一种方法，包括 通过对半导体衬底进行第一离子注入，同时形成静电放电保护器件的第一掺杂区域和大功率器件的第二掺杂区域; 并且通过对所述半导体衬底进行第二离子注入，同时形成所述静电放电保护器件的第三掺杂区域和所述第一低功率器件的第四掺杂区域，所述第一离子注入与所述第二离子注入不同，所述静电放电器件 是与大功率器件不同的器件类型和具有与大功率器件不同结构的静电放电器件。

公开(公告)号：US20110039378A1

公开(公告)日：2011-02-17

申请号：US12541484

申请日：2009-08-14

申请人： Steven Howard Voldman

发明人： Steven Howard Voldman

IPC分类号： H01L21/8238 ,  H01L21/265

CPC分类号： H01L21/823892 ,  H01L21/823814 ,  H01L27/0266 ,  H01L29/66659 ,  H01L29/7835

摘要： A method of forming complementary metal-oxide-silicon logic field effect transistors, high power transistors and electrostatic discharge protection diodes and/or electrostatic discharge protection shunt transistors on the same integrated circuit chip using ion implantations used to fabricate the field effect transistors and high-power transistor to simultaneously fabricate the electrostatic discharge protection diodes and/or electrostatic discharge protection shunt transistors.

摘要翻译： 在同一集成电路芯片上形成互补金属氧化物 - 硅逻辑场效应晶体管，高功率晶体管和静电放电保护二极管和/或静电放电保护分流晶体管的方法，其使用用于制造场效应晶体管和高压晶体管的离子注入， 功率晶体管同时制造静电放电保护二极管和/或静电放电保护并联晶体管。

公开(公告)号：US20090020811A1

公开(公告)日：2009-01-22

申请号：US11778414

申请日：2007-07-16

申请人： Steven Howard Voldman

发明人： Steven Howard Voldman

IPC分类号： H01L27/06 ,  H01L21/8234

CPC分类号： H01L29/7835 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66659

摘要： A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate. The method further includes simultaneously forming a first doped transistor region of a first transistor and a first doped guard-ring region of a guard ring on the semiconductor substrate. The first doped transistor region and the first doped guard-ring region comprise dopants of a first doping polarity. The method further includes simultaneously forming a second doped transistor region of the first transistor and a second doped guard-ring region of the guard ring on the semiconductor substrate. The second doped transistor region and the second doped guard-ring region comprise dopants of the first doping polarity. The second doped guard-ring region is in direct physical contact with the first doped guard-ring region. The guard ring forms a closed loop around the first and second doped transistor regions.

摘要翻译： 半导体结构及其形成方法。 该方法包括提供半导体结构。 半导体结构包括半导体衬底。 该方法还包括在半导体衬底上同时形成第一晶体管的第一掺杂晶体管区域和保护环的第一掺杂保护环区域。 第一掺杂晶体管区域和第一掺杂保护环区域包括第一掺杂极性的掺杂剂。 该方法还包括在半导体衬底上同时形成第一晶体管的第二掺杂晶体管区域和保护环的第二掺杂保护环区域。 第二掺杂晶体管区域和第二掺杂保护环区域包括第一掺杂极性的掺杂剂。 第二掺杂保护环区域与第一掺杂保护环区域直接物理接触。 保护环围绕第一和第二掺杂晶体管区域形成闭环。