公开(公告)号：US20120044732A1

公开(公告)日：2012-02-23

申请号：US13050536

申请日：2011-03-17

申请人： Yu Li ,  Steven Howard Voldman

发明人： Yu Li ,  Steven Howard Voldman

IPC分类号： H01L27/06 ,  H02M1/00 ,  H01L21/76

CPC分类号： H01L23/60 ,  H01L21/76283 ,  H01L21/823481 ,  H01L24/04 ,  H01L27/0277 ,  H01L27/0623 ,  H01L27/0635 ,  H01L2924/01037 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

摘要： An isolated epitaxial modulation device comprises a substrate; a barrier structure formed on the substrate; an isolated epitaxial region formed above the substrate and electrically isolated from the substrate by the barrier structure; a semiconductor device, the semiconductor device located in the isolated epitaxial region; and a modulation network formed on the substrate and electrically coupled to the semiconductor device. The device also comprises a bond pad and a ground pad. The isolated epitaxial region is electrically coupled to at least one of the bond pad and the ground pad. The semiconductor device and the epitaxial modulation network are configured to modulate an input voltage.

摘要翻译： 隔离的外延调制装置包括基板; 形成在所述基板上的阻挡结构; 隔离的外延区，形成在衬底上并通过阻挡结构与衬底电隔离; 半导体器件，位于隔离的外延区域中的半导体器件; 以及形成在所述基板上并且电耦合到所述半导体器件的调制网络。 该装置还包括接合焊盘和接地焊盘。 隔离的外延区电耦合到接合焊盘和接地焊盘中的至少一个。 半导体器件和外延调制网络被配置为调制输入电压。

公开(公告)号：US07541247B2

公开(公告)日：2009-06-02

申请号：US11778414

申请日：2007-07-16

申请人： Steven Howard Voldman

发明人： Steven Howard Voldman

IPC分类号： H01L21/336 ,  H01L21/761

CPC分类号： H01L29/7835 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66659

摘要： A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate. The method further includes simultaneously forming a first doped transistor region of a first transistor and a first doped guard-ring region of a guard ring on the semiconductor substrate. The first doped transistor region and the first doped guard-ring region comprise dopants of a first doping polarity. The method further includes simultaneously forming a second doped transistor region of the first transistor and a second doped guard-ring region of the guard ring on the semiconductor substrate. The second doped transistor region and the second doped guard-ring region comprise dopants of the first doping polarity. The second doped guard-ring region is in direct physical contact with the first doped guard-ring region. The guard ring forms a closed loop around the first and second doped transistor regions.

摘要翻译： 一种半导体结构及其形成方法。 该方法包括提供半导体结构。 半导体结构包括半导体衬底。 该方法还包括在半导体衬底上同时形成第一晶体管的第一掺杂晶体管区域和保护环的第一掺杂保护环区域。 第一掺杂晶体管区域和第一掺杂保护环区域包括第一掺杂极性的掺杂剂。 该方法还包括在半导体衬底上同时形成第一晶体管的第二掺杂晶体管区域和保护环的第二掺杂保护环区域。 第二掺杂晶体管区域和第二掺杂保护环区域包括第一掺杂极性的掺杂剂。 第二掺杂保护环区域与第一掺杂保护环区域直接物理接触。 保护环围绕第一和第二掺杂晶体管区域形成闭环。

公开(公告)号：US20090020818A1

公开(公告)日：2009-01-22

申请号：US11778439

申请日：2007-07-16

申请人： Steven Howard Voldman

发明人： Steven Howard Voldman

IPC分类号： H01L23/62

CPC分类号： H01L29/7391 ,  H01L27/0255

摘要： A semiconductor structure and a method for operating the same. The method includes providing a semiconductor structure. The semiconductor structure includes first, second, third, and fourth doped semiconductor regions. The second doped semiconductor region is in direct physical contact with the first and third doped semiconductor regions. The fourth doped semiconductor region is in direct physical contact with the third doped semiconductor region. The first and second doped semiconductor regions are doped with a first doping polarity. The third and fourth doped semiconductor regions are doped with a second doping polarity. The method further includes (i) electrically coupling the first and fourth doped semiconductor regions to a first node and a second node of the semiconductor structure, respectively, and (ii) electrically charging the first and second nodes to first and second electric potentials, respectively. The first electric potential is different from the second electric potential.

摘要翻译： 半导体结构及其操作方法。 该方法包括提供半导体结构。 半导体结构包括第一，第二，第三和第四掺杂半导体区域。 第二掺杂半导体区域与第一和第三掺杂半导体区域直接物理接触。 第四掺杂半导体区域与第三掺杂半导体区域直接物理接触。 第一和第二掺杂半导体区域掺杂有第一掺杂极性。 第三和第四掺杂半导体区域掺杂有第二掺杂极性。 该方法还包括（i）分别将第一和第四掺杂半导体区域电耦合到半导体结构的第一节点和第二节点，以及（ii）将第一和第二节点分别电充电到第一和第二电位 。 第一电位与第二电位不同。

公开(公告)号：US20090020813A1

公开(公告)日：2009-01-22

申请号：US11778428

申请日：2007-07-16

申请人： Steven Howard Voldman

发明人： Steven Howard Voldman

IPC分类号： H01L29/94 ,  H01L21/8236

CPC分类号： H01L29/0847 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/7834 ,  H01L29/7835

摘要： A semiconductor structure and a method forming the same. The method includes providing a semiconductor structure which includes a semiconductor substrate. The semiconductor substrate includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface. The method further includes simultaneously forming a first doped transistor region of a first transistor and a first doped Source/Drain portion of a second transistor on the semiconductor substrate. The first doped transistor region is not a portion of a Source/Drain region of the first transistor. The first doped transistor region and the first doped Source/Drain portion comprise dopants of a first doping polarity. The method further includes forming a second gate dielectric layer and a second gate electrode region of the second transistor on the semiconductor substrate. The second gate dielectric layer is sandwiched between and electrically insulates the second gate electrode region and the semiconductor substrate.

摘要翻译： 半导体结构及其形成方法。 该方法包括提供包括半导体衬底的半导体结构。 半导体衬底包括限定垂直于顶部衬底表面的参考方向的顶部衬底表面。 该方法还包括在半导体衬底上同时形成第一晶体管的第一掺杂晶体管区域和第二晶体管的第一掺杂源极/漏极部分。 第一掺杂晶体管区域不是第一晶体管的源极/漏极区域的一部分。 第一掺杂晶体管区域和第一掺杂源极/漏极部分包括第一掺杂极性的掺杂剂。 该方法还包括在半导体衬底上形成第二晶体管的第二栅极电介质层和第二栅极电极区域。 第二栅极电介质层被夹在第二栅电极区域和半导体衬底之间并使其电绝缘。

公开(公告)号：US07020857B2

公开(公告)日：2006-03-28

申请号：US10063859

申请日：2002-05-20

申请人： Raminderpal Singh ,  Steven Howard Voldman

发明人： Raminderpal Singh ,  Steven Howard Voldman

IPC分类号： G06F17/50

CPC分类号： H01L21/761 ,  H01L27/0921

摘要： A method and apparatus for analyzing an integrated circuit design for pnpn structures which are likely to latchup or cause injection of noise into the substrate. Once qualifying pnpn structures are identified, the method and apparatus automatically inserts a noise and latchup suppression circuit of the designers' choice into the pnpn structure to eliminate the latchup and/or noise concerns.

摘要翻译： 一种用于分析pnp结构的集成电路设计的方法和装置，其可能闭锁或引起噪声注入衬底。 一旦确定了pnpn结构的符合条件，该方法和装置将设计人员选择的噪声和闭锁抑制电路自动插入到pnpn结构中，以消除闭锁和/或噪声问题。

公开(公告)号：US06826025B2

公开(公告)日：2004-11-30

申请号：US10063857

申请日：2002-05-20

申请人： Raminderpal Singh ,  Steven Howard Voldman

发明人： Raminderpal Singh ,  Steven Howard Voldman

IPC分类号： H02H900

CPC分类号： H01L27/0266

摘要： An integrated circuit having either or both ESD and noise suppression devices that use the inherent resistance in the substrate as an ESD trigger and/or part of the noise suppression.

摘要翻译： 具有ESD和噪声抑制装置中的任一个或两者的集成电路，其使用衬底中的固有电阻作为ESD触发和/或噪声抑制的一部分。

公开(公告)号：US06288880B1

公开(公告)日：2001-09-11

申请号：US09433900

申请日：1999-11-04

申请人： Timothy Scott Hughbanks ,  Neil Leslie Robertson ,  Steven Howard Voldman ,  Albert John Wallash

发明人： Timothy Scott Hughbanks ,  Neil Leslie Robertson ,  Steven Howard Voldman ,  Albert John Wallash

IPC分类号： G11B5127

CPC分类号： G11B5/3903 ,  G11B5/11 ,  G11B5/3103 ,  G11B5/3912 ,  G11B5/40 ,  G11B5/59683 ,  Y10T29/49032

摘要： A magneto-resistive read head having a “parasitic shield” provides an alternative path for currents associated with sparkovers, thus preventing such currents from damaging the read head. The parasitic shield is provided in close proximity to a conventional magnetic shield. The electrical potential of parasitic shield is held essentially equal to the electrical potential of the sensor element. If charges accumulate on the conventional shield, current will flow to the parasitic shield at a lower potential than would be required for current to flow between the conventional shield and the sensor element. Alternatively, conductive spark gap devices are electrically coupled to sensor element leads and to each magnetic shield. Each spark gap device is brought within very close proximity of the substrate to provide an alternative path for charge that builds up between the sensor element and the substrate to be discharged. The ends of the spark gaps that are brought into close proximity of the substrate are preferably configured with high electric field density inducing structures which reduce the voltage required to cause a sparkover between the spark gap device and the substrate.

摘要翻译： 具有“寄生屏蔽”的磁阻式读取头提供了与火花放电相关的电流的替代路径，从而防止这种电流损坏读取头。 寄生屏蔽件靠近传统的磁屏蔽设置。 寄生屏蔽的电位基本上等于传感器元件的电位。 如果电容积累在常规屏蔽上，则电流将以比传统屏蔽和传感器元件之间的电流流动所需的电位更低的电流流向寄生屏蔽。 或者，导电火花隙装置电耦合到传感器元件引线和每个磁屏蔽。 每个火花隙装置被带到非常靠近基板的位置，以提供在传感器元件和待排出的基板之间建立的用于充电的替代路径。 靠近基板的火花隙的端部优选地配置有高电场密度诱导结构，其降低在火花隙装置和基板之间引起火花放电所需的电压。

公开(公告)号：US5761009A

公开(公告)日：1998-06-02

申请号：US480069

申请日：1995-06-07

申请人： Timothy Scott Hughbanks ,  Neil Leslie Robertson ,  Steven Howard Voldman ,  Albert John Wallash

发明人： Timothy Scott Hughbanks ,  Neil Leslie Robertson ,  Steven Howard Voldman ,  Albert John Wallash

IPC分类号： G11B5/10 ,  G11B5/11 ,  G11B5/31 ,  G11B5/39 ,  G11B5/40 ,  G11B5/596 ,  G11B5/127

CPC分类号： G11B5/3903 ,  G11B5/11 ,  G11B5/3912 ,  G11B5/40 ,  G11B5/59683 ,  G11B5/3103 ,  Y10T29/49032

摘要： A magneto-resistive read head having a "parasitic shield" provides an alternative path for currents associated with sparkovers, thus preventing such currents from damaging the read head. The parasitic shield is provided in close proximity to a conventional magnetic shield. The electrical potential of parasitic shield is held essentially equal to the electrical potential of the sensor element. If charges accumulate on the conventional shield, current will flow to the parasitic shield at a lower potential than would be required for current to flow between the conventional shield and the sensor element. Alternatively, conductive spark gap devices are electrically coupled to sensor element leads and to each magnetic shield. Each spark gap device is brought within very close proximity of the substrate to provide an alternative path for charge that builds up between the sensor element and the substrate to be discharged. The ends of the spark gaps that are brought into close proximity of the substrate are preferably configured with high electric field density inducing structures which reduce the voltage required to cause a sparkover between the spark gap device and the substrate.

摘要翻译： 具有“寄生屏蔽”的磁阻式读取头提供了与火花放电相关的电流的替代路径，从而防止这种电流损坏读取头。 寄生屏蔽件靠近传统的磁屏蔽设置。 寄生屏蔽的电位基本上等于传感器元件的电位。 如果电容积累在常规屏蔽上，则电流将以比传统屏蔽和传感器元件之间的电流流动所需的电位更低的电流流向寄生屏蔽。 或者，导电火花隙装置电耦合到传感器元件引线和每个磁屏蔽。 每个火花隙装置被带到非常靠近基板的位置，以提供在传感器元件和待排出的基板之间建立的用于充电的替代路径。 靠近基板的火花隙的端部优选地配置有高电场密度诱导结构，其降低在火花隙装置和基板之间引起火花放电所需的电压。

公开(公告)号：US5731941A

公开(公告)日：1998-03-24

申请号：US525110

申请日：1995-09-08

申请人： Michael John Hargrove ,  Steven Howard Voldman

发明人： Michael John Hargrove ,  Steven Howard Voldman

IPC分类号： H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0251

摘要： An enhanced electrostatic discharge suppression circuit is disclosed for protecting integrated circuit chips from electrostatic discharges or other potentially damaging voltage transients on an input/output pad. The suppression circuit includes a discharge circuit, electrically coupled to the input/output pad, having a diode comprising a diffusion in a substrate well formed in a substrate. The diffusion is connected to the input/output pad of the integrated circuit. A capacitor is locally provided to couple the substrate well to the substrate. The capacitor is sized to maintain the diode in a forward-bias mode during the electrostatic discharge event, thereby facilitating dissipating of the electrostatic discharge. The capacitor comprises a trench capacitor, which depending upon the configuration, may function as a guard ring for the discharge circuit. Certain beneficial parasitic effects are also discussed in association with integration of a trench capacitor into the suppression circuit.

摘要翻译： 公开了一种增强的静电放电抑制电路，用于保护集成电路芯片免受静电放电或输入/输出焊盘上的其他潜在的破坏性电压瞬变。 抑制电路包括电耦合到输入/输出焊盘的放电电路，其具有二极管，该二极管包括在衬底中形成的衬底中的扩散。 扩散连接到集成电路的输入/输出焊盘。 局部提供电容器以将衬底阱与衬底耦合。 电容器的尺寸设计成在静电放电事件期间将二极管保持在正向偏压模式，从而有助于消除静电放电。 电容器包括沟槽电容器，其取决于配置，可用作放电电路的保护环。 还讨论了将沟槽电容器集成到抑制电路中的一些有益的寄生效应。

公开(公告)号：US08193563B2

公开(公告)日：2012-06-05

申请号：US12768877

申请日：2010-04-28

申请人： Jeffrey Peter Gambino ,  Steven Howard Voldman ,  Michael Joseph Zierak

发明人： Jeffrey Peter Gambino ,  Steven Howard Voldman ,  Michael Joseph Zierak

IPC分类号： H01L29/66

CPC分类号： H01L21/76229 ,  H01L21/76232 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7824 ,  H01L29/7835

摘要： A structure and method of fabricating the structure. The structure including: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, the dielectric isolation surrounding a first region and a second region of the substrate, a top surface of the dielectric isolation coplanar with the top surface of the substrate; a dielectric region in the second region of the substrate; the dielectric region extending in the perpendicular direction into the substrate a second distance, the first distance greater than the second distance; and a first device in the first region and a second device in the second region, the first device different from the second device, the dielectric region isolating a first element of the second device from a second element of the second device.

摘要翻译： 一种制造结构的结构和方法。 所述结构包括：在半导体衬底中的介电隔离，所述电介质隔离部在垂直于所述衬底的顶表面的方向上延伸到所述衬底中的第一距离，围绕所述衬底的第一区域和所述第二区域的介电隔离， 介质隔离的顶表面与基底的顶表面共面; 在所述基板的所述第二区域中的介电区域; 所述电介质区域沿垂直方向延伸到所述衬底中第二距离，所述第一距离大于所述第二距离; 以及第一区域中的第一器件和第二区域中的第二器件，所述第一器件不同于所述第二器件，所述电介质区域将所述第二器件的第一元件与所述第二器件的第二元件隔离。