公开(公告)号：US08134308B2

公开(公告)日：2012-03-13

申请号：US12297477

申请日：2007-04-16

申请人： Laurent Guillot ,  Kamel Abouda ,  Philippe Rosado ,  Helmut Henssler ,  Uli Joos ,  Josef Schnell ,  Norbert Stuhler

发明人： Laurent Guillot ,  Kamel Abouda ,  Philippe Rosado ,  Helmut Henssler ,  Uli Joos ,  Josef Schnell ,  Norbert Stuhler

IPC分类号： H05B41/36 ,  H03K17/14

CPC分类号： H05B39/02 ,  H05B39/047 ,  Y02B20/144

摘要： A method is intended to make it possible to drive a PTC electrical load element with a switching unit with the highest possible operational reliability. For this purpose, the electric current is switched off if a predetermined current threshold value is exceeded, the magnitude of the current threshold value being determined from the operating parameters of the load element.

摘要翻译： 一种方法旨在使得能够以具有最高可操作可靠性的开关单元驱动PTC电负载元件成为可能。 为此，如果超过预定的电流阈值，则电流被切断，电流阈值的大小由负载元件的运行参数确定。

公开(公告)号：US08093833B2

公开(公告)日：2012-01-10

申请号：US11661731

申请日：2005-07-14

申请人： Uli Joos ,  Christian Voss ,  Josef Schnell ,  Jochen Zwick

发明人： Uli Joos ,  Christian Voss ,  Josef Schnell ,  Jochen Zwick

IPC分类号： H05B41/36

CPC分类号： H05B33/0851 ,  H05B33/0818 ,  H05B39/047 ,  Y02B20/346

摘要： Disclosed is for controlling a light source by pulse width modulation of a supply voltage. The supply voltage, or a parameter dependent thereon, is measured and the pulse width is controlled as function of the measured value. The supply voltage or parameter is measured at least twice during the pulse and may be cyclically measured. The pulse width of the current or a subsequent pulse is matched to the recorded value of the supply voltage or the parameter. A total value is generated from all of the measured values and compared with a given value and the pulse width of subsequent pulses are matched as function of the difference between the total value and the given value.

摘要翻译： 公开了用于通过电源电压的脉冲宽度调制来控制光源。 测量电源电压或依赖于其的参数，并根据测量值来控制脉冲宽度。 电源电压或参数在脉冲期间至少测量两次，并可循环测量。 电流或后续脉冲的脉冲宽度与电源电压或参数的记录值相匹配。 从所有测量值产生总值，并与给定值进行比较，并将后续脉冲的脉冲宽度作为总值与给定值之差的函数进行匹配。

公开(公告)号：US07808757B2

公开(公告)日：2010-10-05

申请号：US11576135

申请日：2004-09-28

申请人： Laurent Guillott ,  Philippe Rosado ,  Pierre Turpin ,  Francoise Vareilhias ,  Uli Joos ,  Josef Schnell

发明人： Laurent Guillott ,  Philippe Rosado ,  Pierre Turpin ,  Francoise Vareilhias ,  Uli Joos ,  Josef Schnell

IPC分类号： H02H3/093

CPC分类号： H02H3/06 ,  H02H3/006

摘要： Power supply apparatus with overload protection comprising a switch responsive to an input signal for switching between an ON-state for supplying current from a source of power to a load and an OFF-state for interrupting the supply of current to the load, and protection means responsive to an overload condition to switch the switch to the OFF-state. The protection means is responsive to a first overload condition during an initial phase after the switch switches to the ON-state so as to switch the switch back to the OFF-state and maintain the switch in the OFF-state. The protection means is subsequently responsive to a second overload condition if the first overload condition is not detected during the initial phase so as to switch the switch to the OFF-state and subsequently switch the switch back to the ON-state after an interval of time.The protection means is responsive to the current exceeding a first threshold value in detecting the first overload condition, and is responsive to the current exceeding a second threshold value in detecting the second overload condition, the second threshold value being lower than the first threshold value. The protection means is responsive to a temperature of the switch means exceeding a temperature threshold value in detecting at least the first overload condition.

摘要翻译： 具有过载保护的电源设备包括响应于输入信号的开关，用于在从电源提供电流到负载的电流的接通状态和用于中断向负载提供电流的断开状态之间切换;以及保护装置 响应于过载条件将开关切换到OFF状态。 保护装置在开关切换到接通状态之后的初始阶段期间响应于第一过载状况，以将开关切换回关断状态并将开关保持在关闭状态。 如果在初始阶段期间没有检测到第一过载条件，则保护装置随后响应于第二过载状况，以便将开关切换到关闭状态，并且随后在一段时间之后将开关切换回接通状态 。 在检测到第一过载状态时，保护装置响应于超过第一阈值的电流，并且响应于在检测到第二过载状况时超过第二阈值的电流，第二阈值低于第一阈值。 至少在检测到第一过载条件时，保护装置响应于开关装置的温度超过温度阈值。

公开(公告)号：US20100141032A1

公开(公告)日：2010-06-10

申请号：US12519923

申请日：2007-12-14

申请人： Uli Joos ,  Thomas Micheal ,  Josef Schnell ,  Thomas Rössler

发明人： Uli Joos ,  Thomas Micheal ,  Josef Schnell ,  Thomas Rössler

IPC分类号： H02J4/00

CPC分类号： H02M3/156 ,  B60R13/06 ,  H02M2001/008 ,  Y10T307/461 ,  Y10T307/944

摘要： A control unit for triggering a plurality of electric loads with a plurality of input signals, wherein the electric loads are triggered by pulse width modulated signals, and the input signals are PWM signals. A method is described with which the control unit triggers a plurality of electric loads with a plurality of input signals. The control unit includes controllable switching provisions, wherein these switching provisions connect at least one load respectively with one of at least two different PWM inputs. A method is described for triggering a plurality of electric loads with the aid of the control unit.

摘要翻译： 一种用于通过多个输入信号触发多个电负载的控制单元，其中电负载由脉宽调制信号触发，输入信号是PWM信号。 描述了一种控制单元用多个输入信号触发多个电负载的方法。 控制单元包括可控开关设置，其中这些开关设置分别将至少一个负载与至少两个不同PWM输入中的一个连接。 描述了借助于控制单元触发多个电负载的方法。

公开(公告)号：US20080168331A1

公开(公告)日：2008-07-10

申请号：US11650169

申请日：2007-01-05

申请人： Thomas Vogelsang ,  Harald Streif ,  Pete Chlumecky ,  Josef Schnell

发明人： Thomas Vogelsang ,  Harald Streif ,  Pete Chlumecky ,  Josef Schnell

IPC分类号： G11C29/00 ,  G06F11/07

CPC分类号： G11C7/1006 ,  G06F11/1044 ,  G11C2029/0411

摘要： A memory includes an array of memory cells and an error correction code circuit. The error correction code circuit is configured to receive a first portion of a first data word from an external circuit and a second portion of the first data word from the array of memory cells, combine the first portion and the second portion to provide the first data word, and encode the first data word for writing to the array of memory cells.

摘要翻译： 存储器包括存储器单元阵列和纠错码电路。 误差校正码电路被配置为从存储器单元阵列的外部电路和第一数据字的第二部分接收第一数据字的第一部分，组合第一部分和第二部分以提供第一数据 字，并对第一数据字进行编码以写入存储器单元阵列。

公开(公告)号：US20080137472A1

公开(公告)日：2008-06-12

申请号：US11635276

申请日：2006-12-07

申请人： Josef Schnell ,  Farrukh Aquil

发明人： Josef Schnell ,  Farrukh Aquil

IPC分类号： G11C8/18

CPC分类号： G11C11/4076 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225

摘要： One embodiment provides a memory device including a first receiver and a second receiver. The first receiver is configured to receive a single ended clock signal and provide a first clock signal based on the single ended clock signal to provide a memory function. The second receiver is configured to receive a differential clock signal and provide a second clock signal based on the differential clock signal to provide the memory function. Only one of the first receiver and the second receiver is selected to provide the memory function.

摘要翻译： 一个实施例提供了包括第一接收器和第二接收器的存储器件。 第一接收器被配置为接收单端时钟信号，并且基于单端时钟信号提供第一时钟信号以提供存储功能。 第二接收器被配置为接收差分时钟信号，并且基于差分时钟信号提供第二时钟信号以提供存储功能。 选择第一接收机和第二接收机中的一个来提供存储器功能。

公开(公告)号：US20070291572A1

公开(公告)日：2007-12-20

申请号：US11471391

申请日：2006-06-20

申请人： Josef Schnell ,  Farrukh Aquil

发明人： Josef Schnell ,  Farrukh Aquil

IPC分类号： G11C8/00

CPC分类号： G11C8/12 ,  G11C7/22 ,  G11C7/222 ,  G11C8/06 ,  G11C8/18 ,  G11C11/4076

摘要： A memory component includes at least one memory bank array, a first and a second region, a clock tree, and a clock control circuit. The memory component is configured in a semiconductor wafer. The at least one memory bank array is configured such that data is read out of it during a read operation. The clock tree is coupled between the first and second regions and is configured for driving data during the read operation. The clock control circuit is configured within one of the first and second regions and is responsive to read control signals in order to prevent driving the clock tree outside of the read operation.

摘要翻译： 存储器组件包括至少一个存储体阵列，第一和第二区域，时钟树和时钟控制电路。 存储器部件配置在半导体晶片中。 至少一个存储体阵列被配置为使得在读取操作期间从其读出数据。 时钟树耦合在第一和第二区域之间，并被配置为在读取操作期间驱动数据。 时钟控制电路配置在第一和第二区域之一内，并响应于读取控制信号，以防止在读取操作之外驱动时钟树。

公开(公告)号：US20070262765A1

公开(公告)日：2007-11-15

申请号：US11661731

申请日：2005-07-14

申请人： Uli Joos ,  Christian Voss ,  Josef Schnell ,  Jochen Zwick

发明人： Uli Joos ,  Christian Voss ,  Josef Schnell ,  Jochen Zwick

IPC分类号： G05F5/00

CPC分类号： H05B33/0851 ,  H05B33/0818 ,  H05B39/047 ,  Y02B20/346

摘要： Disclosed is for controlling a light source by pulse width modulation of a supply voltage. The supply voltage, or a parameter dependent thereon, is measured and the pulse width is controlled as function of the measured value. The supply voltage or parameter is measured at least twice during the pulse and may be cyclically measured. The pulse width of the current or a subsequent pulse is matched to the recorded value of the supply voltage or the parameter. A total value is generated from all of the measured values and compared with a given value and the pulse width of subsequent pulses are matched as function of the difference between the total value and the given value.

摘要翻译： 公开了用于通过电源电压的脉冲宽度调制来控制光源。 测量电源电压或依赖于其的参数，并根据测量值来控制脉冲宽度。 电源电压或参数在脉冲期间至少测量两次，并可循环测量。 电流或后续脉冲的脉冲宽度与电源电压或参数的记录值相匹配。 从所有测量值产生总值，并与给定值进行比较，并将后续脉冲的脉冲宽度作为总值与给定值之差的函数进行匹配。

公开(公告)号：US20060268632A1

公开(公告)日：2006-11-30

申请号：US11137736

申请日：2005-05-25

申请人： Josef Schnell ,  Ernst Stahl

发明人： Josef Schnell ,  Ernst Stahl

IPC分类号： G11C7/00

CPC分类号： G11C29/02 ,  G01R31/3016 ,  G01R31/31725 ,  G01R31/31726 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028

摘要： An integrated circuit chip including a first delay circuit and a second delay circuit. The first delay circuit has a first delay circuit topology configured to delay a signal a first delay. The second delay circuit has a second delay circuit topology configured to provide a second delay in a circuit loop that is configured to be monitored and provide an oscillating signal. The second delay circuit topology is substantially the same as the first delay circuit topology and the first delay circuit is configured to be trimmed to adjust the first delay based on the second delay and the oscillating signal.

摘要翻译： 一种包括第一延迟电路和第二延迟电路的集成电路芯片。 第一延迟电路具有第一延迟电路拓扑，其被配置为将信号延迟第一延迟。 第二延迟电路具有第二延迟电路拓扑，其被配置为在被配置为被监视并提供振荡信号的电路回路中提供第二延迟。 第二延迟电路拓扑与第一延迟电路拓扑基本相同，并且第一延迟电路被配置为被修整以基于第二延迟和振荡信号调整第一延迟。

公开(公告)号：US20060193194A1

公开(公告)日：2006-08-31

申请号：US11068582

申请日：2005-02-28

申请人： Josef Schnell

发明人： Josef Schnell

IPC分类号： G11C8/00

CPC分类号： G11C11/4076 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012

摘要： Methods and apparatus that determine, at a device (e.g., a DRAM device), a phase difference between two externally supplied timing signals such as a clock signal (CLK) and a data strobe signal (DQS) are provided. Adjustments may be made to timing of one of the signals itself or other internal memory signals that are, perhaps, utilized in circuits controlled by the DQS signal.

摘要翻译： 提供了在设备（例如，DRAM设备）处确定诸如时钟信号（CLK）和数据选通信号（DQS）的两个外部提供的定时信号之间的相位差的方法和装置。 可以对可能在由DQS信号控制的电路中使用的信号本身或其他内部存储器信号之一进行调整。