公开(公告)号：US6035422A

公开(公告)日：2000-03-07

申请号：US857006

申请日：1997-05-15

申请人： William A. Hohl ,  Joseph C. Circello

发明人： William A. Hohl ,  Joseph C. Circello

IPC分类号： G06F11/28 ,  G06F11/22 ,  G06F11/36 ,  G06F11/00

CPC分类号： G06F11/3648 ,  G06F11/3636

摘要： A central processing unit (2) and a debug module (10) execute concurrent operations without requiring a data processor (3) to operate in a special debug mode. The use of a bus (25) to communicate data, address, and control information between a core (9) and debug module (10) allows debug module (10) to have access the same internal registers and memory locations as central processing unit (2). While debug module (10) and central processing unit (2) both have the ability to access the same internal registers and memory locations, central processing unit (2) may not modify a value stored in a plurality of breakpoint registers (50) when an Inhibit Processor Writes to Debug Registers (IPW) bit in a CSR (FIG. 8) of a plurality of control registers (40) is set. The IPW bit may only be modified by a command provided by an external development system (7).

摘要翻译： 中央处理单元（2）和调试模块（10）执行并行操作，而不需要数据处理器（3）以特殊调试模式操作。 使用总线（25）在核心（9）和调试模块（10）之间传送数据，地址和控制信息允许调试模块（10）访问与中央处理单元相同的内部寄存器和存储器位置（ 2）。 虽然调试模块（10）和中央处理单元（2）都具有访问相同的内部寄存器和存储器位置的能力，但是当中央处理单元（2）可以修改存储在多个断点寄存器（50）中的值时， 设置多个控制寄存器（40）的CSR（图8）中的抑制处理器写入调试寄存器（IPW）位。 IPW位只能由外部开发系统（7）提供的命令修改。

公开(公告)号：US5911151A

公开(公告)日：1999-06-08

申请号：US630152

申请日：1996-04-10

申请人： Joseph C. Circello ,  James N. Hardage, Jr. ,  Glen A. Harris

发明人： Joseph C. Circello ,  James N. Hardage, Jr. ,  Glen A. Harris

IPC分类号： G06F9/315 ,  G06F9/32 ,  G06F13/28

CPC分类号： G06F9/30032 ,  G06F9/325

摘要： A computer processor (110) automatically generates block-size operand references during execution of standard instructions. As such a standard instruction is executed, the processor (110) continually examines the number of bytes to be moved (342) and the relative alignment of the operand address (352). At any time during instruction execution, if the operand address is zero modulo the block size, and at least a block sized number of bytes remain to be moved (354), the operand transfer is marked as a block-sized reference.This provides a convenient method for generating block-sized memory references to/from the targeted address space, independent of cache modes such as copyback, write-through, or non-cacheable. This may produce burst accesses, maximizing performance of the data transfer. Additionally, cache memory writes can be optimized to avoid cache line fill reads.The result is that such standard instructions become the optimal method of transferring data from a source to a destination without the need for special instructions.

摘要翻译： 计算机处理器（110）在执行标准指令期间自动生成块大小的操作数引用。 当执行这样的标准指令时，处理器（110）连续检查要移动的字节数（342）和操作数地址（352）的相对对齐。 在指令执行期间的任何时间，如果操作数地址为零模块的块大小，并且至少一个块大小的字节数仍然被移动（354），则操作数传输被标记为块大小的引用。 这提供了一种方便的方法，用于生成针对目标地址空间的块大小的内存引用，与缓存模式（如copyback，直写或非高速缓存）无关。 这可能会产生突发访问，从而最大限度地提高数据传输的性能。 此外，可以优化高速缓存存储器写入以避免高速缓存行填充读取。 结果是这样的标准指令成为将数据从源传送到目的地而不需要特殊指令的最佳方法。

公开(公告)号：US5872940A

公开(公告)日：1999-02-16

申请号：US627669

申请日：1996-04-01

申请人： Joseph C. Circello ,  James G. Gay ,  Clinton T. Glover ,  Kevin M. Traynor

发明人： Joseph C. Circello ,  James G. Gay ,  Clinton T. Glover ,  Kevin M. Traynor

IPC分类号： G06F13/14 ,  G06F13/16 ,  G06F13/38

CPC分类号： G06F13/1694

摘要： A system bus controller (103) within a processor (101) includes programmable logic for different modes of chip enable signals on a per-address-space basis. This allows for a "glueless" interface (107) between the processor (101) and different types of external devices (111, 112, 113), such as memory devices. A chip select register value 604, 608, 612 is preprogrammed with respect to each external device coupled to the processor (101). This preprogrammed register value 604, 608, 612 is used by the system bus controller (103) to uniquely configure a read/write access signal to be sent to each of the external devices (111, 112, 113).

摘要翻译： 处理器（101）内的系统总线控制器（103）包括用于每个地址空间的不同模式的芯片使能信号的可编程逻辑。 这允许在处理器（101）和不同类型的外部设备（111,112,113）之间的诸如存储器设备之间的“无胶粘”接口（107）。 相对于耦合到处理器（101）的每个外部设备，对芯片选择寄存器值604,608,612进行预编程。 系统总线控制器（103）使用该预编程寄存器值604,608,612来唯一地配置要发送到每个外部设备（111,112,113）的读/写访问信号。

公开(公告)号：US5666509A

公开(公告)日：1997-09-09

申请号：US216998

申请日：1994-03-24

申请人： Daniel M. McCarthy ,  Joseph C. Circello ,  Richard Duerden ,  Gregory C. Edgington ,  Cliff L. Parrott ,  William B. Ledbetter, Jr.

发明人： Daniel M. McCarthy ,  Joseph C. Circello ,  Richard Duerden ,  Gregory C. Edgington ,  Cliff L. Parrott ,  William B. Ledbetter, Jr.

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F12/10

CPC分类号： G06F12/0888 ,  G06F9/3861 ,  G06F12/0804 ,  G06F12/1027

摘要： A processor (10) has a data cache unit (16) wherein the data cache unit includes a memory management unit (MMU) (32). The MMU contains memory locations within transparent translation registers (TTRs), an address translation cache (40), or a table walk controller (42) which store or generate cache mode (CM) bits which indicate whether a memory access (i.e., a write operation) is precise or imprecise. Precise operations require that a first write operation or bus write instruction be executed with no other operationsnstructions executing until the first operation/instruction completes with or without a fault. Imprecise operations are operations/instruction which may be queued, partially performed, or execution simultaneously with other instructions regardless of faults or bus write operations. By allowing the logical address to determine whether the bus write operation is precise or imprecise, a large amount of system flexibility is achieved.

摘要翻译： 处理器（10）具有数据高速缓存单元（16），其中数据高速缓存单元包括存储器管理单元（MMU）（32）。 MMU包含存储或产生高速缓存模式（CM）位的透明转换寄存器（TTR），地址转换高速缓冲存储器（40）或表格移动控制器（42）内的存储单元，其指示存储器访问（即，写入 操作）精确或不准确。 精确的操作要求执行第一个写入操作或总线写入指令，直到第一个操作/指令完成或不存在故障，才执行其他操作/指令。 不精确的操作是可以与其他指令同时排队，部分执行或执行的操作/指令，而不管故障或总线写操作。 通过允许逻辑地址来确定总线写操作是精确还是不准确，实现了大量的系统灵活性。

公开(公告)号：US5592493A

公开(公告)日：1997-01-07

申请号：US304968

申请日：1994-09-13

申请人： Alfred L. Crouch ,  Matthew D. Pressly ,  Joseph C. Circello ,  Richard Duerden

发明人： Alfred L. Crouch ,  Matthew D. Pressly ,  Joseph C. Circello ,  Richard Duerden

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318536 ,  G01R31/318558

摘要： A scan chain architecture which has a controller (10), and a multiplexer (24) is used to route test data through functional units (12, 14, 16, 18, 20, and 22). The controller (10) receives as input a serial data stream from an STDI terminal and demultiplexes this data stream to one of the functional units (six functional units are illustrated in FIG. 1). Each of the functional units is considered as one scan chain and therefore FIG. 1 has six scan chains (one for each functional unit). In addition, a seventh scan chain couples all output flip-flops in each of the functional units together between an output of the MUX (24) and the STDO terminal/pin. Therefore, a serial scan of a data stream can be done through one functional unit, the multiplexer (24) and into the output flip-flops of each function unit to make testing easier to set-up. In addition, various new scan chain cells and low power methods are used herein.

摘要翻译： 具有控制器（10）和多路复用器（24）的扫描链架构用于通过功能单元（12,14,16,18,20和22）路由测试数据。 控制器（10）作为输入接收来自STDI终端的串行数据流，并将该数据流解复用于功能单元之一（图1中示出了六个功能单元）。 每个功能单元被认为是一个扫描链，因此， 1具有6个扫描链（每个功能单元一个）。 此外，第七扫描链将MUX（24）的输出和STDO端子/引脚之间的每个功能单元中的所有输出触发器耦合在一起。 因此，可以通过一个功能单元，多路复用器（24）和每个功能单元的输出触发器来完成数据流的串行扫描，以使测试更容易设置。 此外，在本文中使用各种新的扫描链单元和低功率方法。

公开(公告)号：US5530804A

公开(公告)日：1996-06-25

申请号：US242767

申请日：1994-05-16

申请人： Gregory C. Edgington ,  Joseph C. Circello ,  Daniel M. McCarthy ,  Richard Duerden

发明人： Gregory C. Edgington ,  Joseph C. Circello ,  Daniel M. McCarthy ,  Richard Duerden

IPC分类号： G06F11/26 ,  G06F11/267 ,  G06F11/36

CPC分类号： G06F11/3648 ,  G06F11/2236 ,  G06F11/261 ,  G06F12/10

摘要： A processor (10) has two modes of operation. One mode of operation is a normal mode of operation wherein the processor (10) accesses user address space or supervisor address space to perform a predetermined function. The other mode of operation is referred to as a debug, test, or emulator mode of operation and is entered via an exception/interrupt. The debug mode is an alternate operational mode of the processor (10) which has a unique debug address space which executes instructions from the normal instruction set of the processor (10). Furthermore, the debug mode of operation does not adversely affect the state of the normal mode of operation while executing debug, test, and emulation commands at normal processor speed. The debug mode is totally non-destructive and non-obtrusive to the "suspended" normal mode of operation. While in debug mode, the existing processor pipelines, bus interface, etc. are utilized.

摘要翻译： 处理器（10）具有两种操作模式。 一种操作模式是正常操作模式，其中处理器（10）访问用户地址空间或管理员地址空间以执行预定功能。 其他操作模式被称为调试，测试或仿真器操作模式，并通过异常/中断输入。 调试模式是处理器（10）的替代操作模式，其具有独特的调试地址空间，其执行来自处理器（10）的正常指令集的指令。 此外，在以正常的处理器速度执行调试，测试和仿真命令时，调试操作模式不会对正常操作模式的状态产生不利影响。 调试模式是完全非破坏性的，不违反“暂停”正常操作模式。 在调试模式下，利用现有的处理器管线，总线接口等。

公开(公告)号：US5471625A

公开(公告)日：1995-11-28

申请号：US125851

申请日：1993-09-27

申请人： Gary A. Mussemann ,  Joseph C. Circello ,  James G. Gay

发明人： Gary A. Mussemann ,  Joseph C. Circello ,  James G. Gay

IPC分类号： G06F1/32 ,  G06F13/00

CPC分类号： G06F1/3203

摘要： A method and apparatus for placing a data processor (12) into a low-power mode of operation using a system (10). The system (10) has a processor (12). The processor (12) has access to a bus (18). The bus (18) is coupled to a bus controller (14). The processor (12) sends a broadcast cycle out through the bus (18) when the processor (12) desires to enter a low-power mode of operation. The bus controller (14) determines that the broadcast cycle has been sent on the bus (18). The bus controller (14) waits a predetermined amount of time to process the low-power request and grants permission to the processor (12) to enter the low-power mode via the communication of a transmission termination signal. The processor (12) conditionally drives either logic ones or a tri-state value onto the bus (18) depending upon whether or not the processor (12) has been granted ownership of the bus (18).

摘要翻译： 一种用于使用系统（10）将数据处理器（12）置于低功率操作模式的方法和装置。 系统（10）具有处理器（12）。 处理器（12）可访问总线（18）。 总线（18）耦合到总线控制器（14）。 当处理器（12）希望进入低功率操作模式时，处理器（12）通过总线（18）发送广播周期。 总线控制器（14）确定广播周期已经在总线（18）上发送。 总线控制器（14）等待预定量的时间来处理低功率请求，并通过传输终止信号的通信向处理器（12）授予许可以进入低功率模式。 处理器（12）根据处理器（12）是否被授予总线（18）的所有权，有条件地将逻辑1或三态值驱动到总线（18）上。

公开(公告)号：US5101341A

公开(公告)日：1992-03-31

申请号：US241111

申请日：1988-09-02

申请人： Joseph C. Circello ,  Richard H. Duerden ,  Roger W. Luce ,  Ralph H. Olson

发明人： Joseph C. Circello ,  Richard H. Duerden ,  Roger W. Luce ,  Ralph H. Olson

IPC分类号： G06F9/30 ,  G06F9/315 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08

CPC分类号： G06F9/382 ,  G06F12/0848 ,  G06F9/30032 ,  G06F9/30054 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/325 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3889

摘要： A system and technique for providing early decoding of complex instructions in a pipelined processor uses a programmed logic array to decode instruction segments and loads both the instruction bits and the associated predecoded bits into a FIFO buffer to accumulate a plurality of such entries. Meanwhile, an operand execute pipeline retrieves such entries from the FIFO buffer as needed, using the predecoded instruction bits to rapidly decode and execute the instructions at rates determined by the instructions themselves. Delays due to cache misses are substantially or entirely masked, as the instructions and associated predecoded bits are loaded into the FIFO buffer more rapidly than they are retrieved from it, except during cache misses. A method is described for increasing the effective speed of executing a three operand construct. Another method is disclosed for increasing the effective speed of executing a loop containing a branch instruction by scanning the predecoded bits in establishing a link between successive instructions.

摘要翻译： 用于在流水线处理器中提供复杂指令的早期解码的系统和技术使用编程逻辑阵列来对指令段进行解码，并将指令位和相关联的预解码位加载到FIFO缓冲器中以累积多个这样的条目。 同时，操作数执行管道根据需要从FIFO缓冲器检索这些条目，使用预解码指令位以由指令本身确定的速率快速解码和执行指令。 由于高速缓存未命中的延迟基本上或完全被屏蔽，因为除了在高速缓存未命中之外，指令和相关联的预解码位被加载到FIFO缓冲器中比它们从其中检索得更快。 描述了一种用于增加执行三操作数构造的有效速度的方法。 公开了一种用于通过在建立连续指令之间的链接的情况下扫描预解码比特来增加执行包含分支指令的循环的有效速度的方法。

公开(公告)号：US4538238A

公开(公告)日：1985-08-27

申请号：US458794

申请日：1983-01-18

申请人： Joseph C. Circello ,  Russell W. Guenthner

发明人： Joseph C. Circello ,  Russell W. Guenthner

IPC分类号： G06F7/72 ,  G06F7/38

CPC分类号： G06F7/727

摘要： Method and apparatus for calculating the residue of a signed binary number of "n" bits with respect to a given check base m where m=2.sup.b -1. The bits of the binary number excluding the sign bit are partitioned into number segments, each of b bits starting with the least significant bit. If (n-1) is not an even multiple of b, higher order bit positions of the number segment containing the next most significant bit of the binary number are filled with logical zeros. A sign segment of b bits is formed. Both number and sign segments have boundaries. The bit position in the sign segment relative to a sign segment boundary which corresponds to the bit position of the sign bit "s" relative to the nearest boundary of a number segment is filled with a logical zero. All other bit positions of the sign segment are filled with the sign bit. The number and sign segments are applied to carry save adders to reduce the number segments and sign segment to a single sum segment and a single rotated carry segment. A rotated carry segment is a carry segment produced by a carry save adder, the most significant bit of which becomes the least significant bit of the rotated carry segment. The other bits of the carry segment and their significance are increased by one in the rotated carry segment. Carry segments produced by carry save adders of one level are converted to rotated carry segments before being applied to a carry save or full adder of a lower level. The single sum segment and single rotated carry segment produced by the lowest level carry save adder is applied to a one's complement adder. The b bit output of the one's complement adder is the residue of the signed binary number to the check base (2.sup.b -1).

摘要翻译： 用于计算相对于m = 2b-1的给定检验基数m的带符号二进制数“n”位的残差的方法和装置。 除符号位之外的二进制数的位被分割为数字段，每个b位以最低有效位开始。 如果（n-1）不是b的偶数倍，则包含二进制数的下一个最高有效位的数字段的高位位置被填充有逻辑0。 形成b位的符号段。 数字和符号段都有边界。 符号段相对于符号段边界相对于符号位“s”相对于数字段的最近边界的位位置的位位置用逻辑0填充。 符号段的所有其他位位置都用符号位填充。 数字和符号段被应用于携带保存加法器以减少数字段并将段标记到单个和段和单个旋转进位段。 旋转的进位段是由进位保存加法器产生的进位段，其最高有效位变为旋转进位段的最低有效位。 进位段的其他位及其重要性在旋转进位段增加1。 由一个级别的进位保存加法器产生的进位段在应用于较低级别的进位保存或全加器之前被转换为旋转的进位段。 由最低电平进位保存加法器产生的单个和段和单个旋转进位段应用于一个补码加法器。 补码加法器的b位输出是到校验基（2b-1）的带符号二进制数的残差。