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    Data input and output circuits for multi-data rate operation
    51.
    发明授权
    Data input and output circuits for multi-data rate operation 失效
    用于多数据速率操作的数据输入和输出电路

    公开(公告)号：US07061941B1

    公开(公告)日：2006-06-13

    申请号：US09724306

    申请日：2000-11-28

    申请人： Hua Zheng

    发明人： Hua Zheng

    IPC分类号： H04L12/50 ,  H04Q11/00 ,  G11C8/00

    CPC分类号： G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  H04Q2213/13103 ,  H04Q2213/13106 ,  H04Q2213/13292

    摘要： Data input and output circuits that support multi data rate and a number of timing schemes. In one design, a data output circuit includes an input multiplexer, data latches, an output multiplexer, and at least one output driver. The input multiplexer receives a set of data bits in a first order (e.g., odd and even) and provides the data bits in a second order (e.g., first and second). The data latches can latch the data bits with (1) a latch signal to satisfy memory access timing requirements and (2) a data write clock signal to satisfy output timing requirements. The output multiplexer multiplexes the latched data bits to provide time multiplexed data bits. The output driver(s) provide signal drive for the time multiplexed data bits. Clock signals with various timing characteristics can be used to allow the data output circuit to satisfy various timing requirements.

    摘要翻译： 数据输入和输出电路，支持多种数据速率和多种时序方案。 在一种设计中，数据输出电路包括输入多路复用器，数据锁存器，输出多路复用器和至少一个输出驱动器。 输入多路复用器以第一顺序（例如，奇数和偶数）接收一组数据位，并以二阶（例如，第一和第二）提供数据位。 数据锁存器可以用（1）锁存信号锁存数据位，以满足存储器访问时序要求，以及（2）数据写时钟信号以满足输出时序要求。 输出多路复用多路复用锁存数据位以提供时间复用数据位。 输出驱动器为时间复用数据位提供信号驱动。 具有各种定时特性的时钟信号可用于允许数据输出电路满足各种定时要求。

    High speed test system for a memory device
    52.
    发明授权
    High speed test system for a memory device 有权
    高速测试系统用于存储器件

    公开(公告)号：US06550026B1

    公开(公告)日：2003-04-15

    申请号：US09724346

    申请日：2000-11-27

    申请人： Jeffrey P. Wright ,  Hua Zheng ,  Paul M. Fuller

    发明人： Jeffrey P. Wright ,  Hua Zheng ,  Paul M. Fuller

    IPC分类号： G11C2900

    CPC分类号： G11C29/38 ,  G11C29/34

    摘要： A memory device requires a minimum of two input/output lines from an external testing device to be coupled thereto. A first DQ line from the memory device provides a direct data path from the array so that the external tester can read data from the array at the maximum speed of the memory device. Test mode circuitry for multiplexing and comparing multiple DQ lines during address compression mode is coupled to two or more DQ lines, including the first DQ line. The compression mode testing circuitry can include on-chip comparators that compare the data simultaneously written to, and read from, the memory device. The comparison circuitry outputs a data test flag indicating whether or not the data read from the memory device matches. The test flag is output through a multiplexer to a second DQ line. As a result, the speed of the device can be tested from the first DQ line, while the results of on-chip comparison can be sampled at the second DQ line. The compare circuitry compares not only bits of a given data word, but also at least one bit from another data word. Therefore, rather than employing two compare circuits that compare first and second data words, and a third compare circuit that compares the results of the first two compare circuits, the present invention avoids the need for the third compare circuit by comparing the first data word in a first compare circuit with at least one bit from the second data word.

    摘要翻译： 存储器件需要至少两个来自外部测试装置的输入/输出线与其耦合。 来自存储器件的第一条DQ线提供了阵列的直接数据路径，以便外部测试器可以以存储器件的最大速度从阵列中读取数据。 用于在地址压缩模式期间复用和比较多个DQ线的测试模式电路被耦合到两条或更多条DQ线，包括第一条DQ线。 压缩模式测试电路可以包括片上比较器，其比较同时写入存储器件和从存储器件读取的数据。 比较电路输出指示从存储器件读取的数据是否匹配的数据测试标志。 测试标志通过多路复用器输出到第二个DQ线。 因此，可以从第一个DQ线路测试器件的速度，而可以在第二个DQ线路上对片上比较的结果进行采样。比较电路不仅比较给定数据字的位，还可以比较给定数据字的位 来自另一数据字的至少一位。 因此，不是采用比较第一和第二数据字的两个比较电路，而是比较前两个比较电路的结果的第三比较电路，本发明通过比较第一和第二数据字的第一数据字， 具有来自第二数据字的至少一位的第一比较电路。

    Memory array architecture for multi-data rate operation
    54.
    发明授权
    Memory array architecture for multi-data rate operation 有权
    用于多数据速率操作的内存阵列架构

    公开(公告)号：US6094396A

    公开(公告)日：2000-07-25

    申请号：US195269

    申请日：1998-11-18

    申请人： Hua Zheng

    发明人： Hua Zheng

    IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C11/4096 ,  G11C8/00

    CPC分类号： G11C7/1096 ,  G11C11/4096 ,  G11C7/00 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078

    摘要： A memory array architecture (which can be used to implement a memory device and other circuits having an embedded memory array) supports multi-data rate operation. The memory device includes at least one memory array and at least one sense amplifier arrays. Each memory array is partitioned into a number of substantially similar segments. Each segment is associated with at least one local I/O lines. Each local I/O line has a length that is a portion of a length of the memory array. By partitioning the memory array, the supporting circuitry (e.g., the sense amplifier array), and the local I/O lines into segments, access of multiple data bits can be achieved without having to incur a significant "die penalty."

    摘要翻译： 存储器阵列架构（可用于实现存储器件和具有嵌入式存储器阵列的其它电路）支持多数据速率操作。 存储器件包括至少一个存储器阵列和至少一个读出放大器阵列。 每个存储器阵列被划分成多个基本相似的段。 每个段与至少一个本地I / O线相关联。 每个本地I / O线的长度是存储器阵列长度的一部分。 通过将存储器阵列，支持电路（例如，读出放大器阵列）和本地I / O线分割成段，可以实现多个数据位的访问，而不必产生显着的“罚球”。

    Method and circuit for triggering column select line for write operations
    55.
    发明授权
    Method and circuit for triggering column select line for write operations 有权
    触发列选择行写入操作的方法和电路

    公开(公告)号：US6061292A

    公开(公告)日：2000-05-09

    申请号：US195268

    申请日：1998-11-18

    申请人： Teng Su ,  Hua Zheng ,  Kamin Fei

    发明人： Teng Su ,  Hua Zheng ,  Kamin Fei

    IPC分类号： G11C7/22 ,  G11C8/10 ,  G11C8/00

    CPC分类号： G11C7/1066 ,  G11C7/22 ,  G11C8/10

    摘要： Methods and circuits for triggering column select line for write operations in a multiple data rate (e.g., a double data rate) operation. A memory device includes a memory array that stores data values, an address logic circuit that generates an address for the memory array, and a column decoder. The column decoder couples to the address logic circuit and the memory array. The column decoder receives either a data strobe input signal (DQS) or a clock signal (CLK), or both, and activates a column select line for the memory array in response to one of the input signal(s).

    摘要翻译： 用于以多数据速率（例如，双数据速率）操作来触发用于写入操作的列选择线的方法和电路。 存储器件包括存储数据值的存储器阵列，产生存储器阵列的地址的地址逻辑电路和列解码器。 列解码器耦合到地址逻辑电路和存储器阵列。 列解码器接收数据选通输入信号（DQS）或时钟信号（CLK）或两者，并且响应于输入信号中的一个激活存储器阵列的列选择线。

    System for improved memory cell access
    56.
    发明授权
    System for improved memory cell access 失效

    公开(公告)号：US5959933A

    公开(公告)日：1999-09-28

    申请号：US999865

    申请日：1997-04-18

    申请人： Hua Zheng

    发明人： Hua Zheng

    IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C11/4096 ,  G11C8/00

    CPC分类号： G11C7/1048 ,  G11C11/4096

    摘要： A voltage booting circuit for booting the switching signal applied to a column access passgate is employed to reduce the voltage drop across the passgate. Reduction of the voltage dropped across the passgate results in faster read and write times and improved noise margin. In one application the booted voltage is used only during a write operation, but not during a read. In another application, the booted voltage is used during both operations.

    Multiple bank memory with auto refresh to specified bank
    57.
    发明授权
    Multiple bank memory with auto refresh to specified bank 失效
    具有自动刷新到指定银行的多个存储区

    公开(公告)号：US5627791A

    公开(公告)日：1997-05-06

    申请号：US602593

    申请日：1996-02-16

    申请人： Jeffrey P. Wright ,  Hua Zheng

    发明人： Jeffrey P. Wright ,  Hua Zheng

    IPC分类号： G11C11/407 ,  G11C11/403 ,  G11C11/406 ,  G11C7/00

    CPC分类号： G11C11/406

    摘要： A synchronous random access memory, such as a synchronous dynamic random access memory or a synchronous graphic random access memory, is responsive to command signals and includes multiple bank memory arrays. A command decoder/controller responds to command signals to initiate, in a first system clock cycle, an auto-refresh command controlling an auto refresh operation to a specified one of the multiple bank memory arrays.

    摘要翻译： 诸如同步动态随机存取存储器或同步图形随机存取存储器的同步随机存取存储器响应命令信号并且包括多个存储体存储器阵列。 命令解码器/控制器响应于命令信号，以在第一系统时钟周期内启动控制对多个存储体存储器阵列中指定的一个的自动刷新操作的自动刷新命令。