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    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICES
    51.
    发明申请
    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICES 有权
    非易失性半导体存储器件

    公开(公告)号：US20090294838A1

    公开(公告)日：2009-12-03

    申请号：US12503354

    申请日：2009-07-15

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byoung-Woo Ye

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byoung-Woo Ye

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11521 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/792

    摘要： A non-volatile memory device includes a tunneling insulating layer on a semiconductor substrate, a charge storage layer, a blocking insulating layer, and a gate electrode. The charge storage layer is on the tunnel insulating layer and has a smaller band gap than the tunnel insulating layer and has a greater band gap than the semiconductor substrate. The blocking insulating layer is on the charge storage layer and has a greater band gap than the charge storage layer and has a smaller band gap than the tunnel insulating layer. The gate electrode is on the blocking insulating layer.

    摘要翻译： 非易失性存储器件包括在半导体衬底上的隧道绝缘层，电荷存储层，阻挡绝缘层和栅电极。 电荷存储层在隧道绝缘层上，并且具有比隧道绝缘层更小的带隙，并且具有比半导体衬底更大的带隙。 阻挡绝缘层位于电荷存储层上，并且具有比电荷存储层更大的带隙，并且具有比隧道绝缘层更小的带隙。 栅电极位于阻挡绝缘层上。

    Non-volatile semiconductor memory devices
    53.
    发明授权
    Non-volatile semiconductor memory devices 有权
    非易失性半导体存储器件

    公开(公告)号：US07253467B2

    公开(公告)日：2007-08-07

    申请号：US10795537

    申请日：2004-03-08

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byoung-Woo Ye

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byoung-Woo Ye

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11521 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/792

    摘要： A non-volatile memory device includes a semiconductor substrate, a tunneling insulating layer, a charge storage layer, a blocking insulating layer, and a gate electrode. The tunneling insulating layer is on the substrate and has a first dielectric constant. The charge storage layer is on the tunneling insulating layer. The blocking insulating layer is on the charge storage layer and has a second dielectric constant which is greater than the first dielectric constant of the tunneling insulting layer. The gate electrode is on the blocking insulating layer, and at least a portion of the gate electrode adjacent to the blocking layer has a higher work-function than polysilicon.

    摘要翻译： 非易失性存储器件包括半导体衬底，隧道绝缘层，电荷存储层，阻挡绝缘层和栅电极。 隧道绝缘层在衬底上并具有第一介电常数。 电荷存储层位于隧道绝缘层上。 阻挡绝缘层在电荷存储层上，并且具有大于隧道绝缘层的第一介电常数的第二介电常数。 栅电极在阻挡绝缘层上，与阻挡层相邻的栅电极的至少一部分具有比多晶硅更高的功函数。

    Nonvolatile memory devices and methods of making the same
    55.
    发明申请
    Nonvolatile memory devices and methods of making the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US20060220098A1

    公开(公告)日：2006-10-05

    申请号：US11363326

    申请日：2006-02-27

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi

    IPC分类号： H01L29/788

    CPC分类号： H01L27/1052 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524

    摘要： Nonvolatile memory devices and methods of making the same are described. A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. Each of the transistors includes a channel region and source/drain regions. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers.

    摘要翻译： 描述了非易失性存储器件及其制造方法。 非易失性存储器件包括串选择晶体管，多个存储单元晶体管和与串选择晶体管和多个存储单元晶体管串联电连接的接地选择晶体管。 每个晶体管包括沟道区和源极/漏极区。 在存储单元晶体管的沟道和源极/漏极区的边界处形成第一杂质层。 相对于存储单元晶体管的源/漏区，第一杂质层掺杂有相反导电类型的杂质。 第二杂质层形成在串选择晶体管的沟道和漏极区之间的边界处，并且在地选择晶体管的沟道和源极区之间形成。 第二杂质层掺杂有与第一杂质层相同的导电类型杂质，并且具有比第一杂质层更高的杂质浓度。

    Non-volatile memory device and method for fabricating the same
    57.
    发明授权
    Non-volatile memory device and method for fabricating the same 有权

    公开(公告)号：US06677639B2

    公开(公告)日：2004-01-13

    申请号：US10188389

    申请日：2002-07-01

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byung-Kwan You ,  Sung-Hoi Hur

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byung-Kwan You ,  Sung-Hoi Hur

    IPC分类号： H01L2976

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： A non-volatile memory device and fabrication method thereof are provided. A floating region is formed on an active region on a substrate. Trenches define the active region. The floating region is made of an ONO layer. A gate electrode is formed on the floating region. A mask is formed on the gate electrode. A thermal oxidation is performed to make a sidewall oxide and a trench oxide on the sidewall of the gate electrode and the trench, respectively. As a result, the widths of the gate electrode and the active region become less than the width of the floating region, thereby forming protrusions at ends of the floating region. Isolation regions are formed in the trenches and include the sidewall oxide and the trench oxide. The isolation regions surround the protrusions. As a result, electric field induced on the sidewall of the floating region is decreased. Moreover, the thermal oxidation cures any damage to the sidewalls of the floating region. Accordingly, leakage current can be substantially suppressed at the boundary region between the isolation region and the floating region.

    Method of forming non-volatile memory having floating trap type device
    58.
    发明授权
    Method of forming non-volatile memory having floating trap type device 失效
    形成具有浮动陷阱型装置的非易失性存储器的方法

    公开(公告)号：US06677200B2

    公开(公告)日：2004-01-13

    申请号：US10194182

    申请日：2002-07-12

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Sung-Hoi Hur

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Sung-Hoi Hur

    IPC分类号： H01L213366

    CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L29/66833 ,  Y10S438/954

    摘要： A method of forming a non-volatile memory having a floating trap-type device is disclosed in the present invention. In the method, a relatively thick thermal oxide layer is formed at a semiconductor substrate and patterned to leave a thick thermal oxide pattern at a high-voltage region (a high-voltage region defining step). An oxide-nitride-oxide (ONO) layer is formed over substantially the entire surface (the substantial surface) of the semiconductor substrate and patterned to leave an ONO pattern at a cell memory region (a cell memory region defining step). After the high-voltage region defining step and the cell memory region defining step, a thermal oxidizing process is performed with respect to the semiconductor substrate where a low-voltage region is exposed, thereby forming a relatively thin gate insulation layer for a low-voltage type device (a low-voltage region defining region).

    摘要翻译： 在本发明中公开了形成具有浮动陷阱型装置的非易失性存储器的方法。 在该方法中，在半导体衬底上形成相对较厚的热氧化物层，并将其图案化以在高电压区域（高电压区域限定步骤）处留下厚的热氧化物图案。 在半导体衬底的基本上整个表面（基本表面）上形成氧化物 - 氧化物（ONO）层，并将其图案化以在单元存储区（单元存储区定义步骤）处留下ONO图案。 在高电压区域定义步骤和电池存储区域限定步骤之后，对于暴露低电压区域的半导体衬底进行热氧化处理，从而形成用于低电压的较薄的栅极绝缘层 （低电压区域限定区域）。

    Memory devices having semiconductor patterns on a substrate and methods of manufacturing the same
    59.
    发明授权
    Memory devices having semiconductor patterns on a substrate and methods of manufacturing the same 有权
    在衬底上具有半导体图案的存储器件及其制造方法

    公开(公告)号：US09324727B2

    公开(公告)日：2016-04-26

    申请号：US14176332

    申请日：2014-02-10

    申请人： Chang-Hyun Lee ,  Hyun-Jung Kim ,  Dong-Hoon Jang ,  Albert Fayrushin

    发明人： Chang-Hyun Lee ,  Hyun-Jung Kim ,  Dong-Hoon Jang ,  Albert Fayrushin

    IPC分类号： H01L27/115 ,  H01L21/762 ,  H01L23/48 ,  H01L29/788

    CPC分类号： H01L27/11582 ,  H01L21/76224 ,  H01L27/11551 ,  H01L27/11565 ,  H01L29/7889

    摘要： A memory device may include a plurality of semiconductor patterns on a substrate including a plurality of first impurity regions doped at a first impurity concentration, a plurality of second impurity regions at portions of the substrate contacting the plurality of semiconductor patterns and doped at a second impurity concentration, a plurality of channel patterns on the plurality of semiconductor patterns, a plurality of gate structures, a plurality of third impurity regions at portions of the substrate adjacent to end portions of the plurality of gate structures, and a plurality of fourth impurity regions at portions of the substrate between the second and third impurity regions and between adjacent second impurity regions. The plurality of fourth impurity regions may be doped at a third impurity concentration which may be lower than the first and second impurity concentrations.

    摘要翻译： 存储器件可以包括在衬底上的多个半导体图案，其包括以第一杂质浓度掺杂的多个第一杂质区域，在与多个半导体图案接触并且以第二杂质掺杂的衬底的部分处的多个第二杂质区域 浓度，多个半导体图案上的多个沟道图案，多个栅极结构，在与多个栅极结构的端部相邻的基板的部分处的多个第三杂质区域，以及多个第四杂质区域 在第二和第三杂质区之间和相邻的第二杂质区之间的衬底的部分。 可以在可以低于第一和第二杂质浓度的第三杂质浓度下掺杂多个第四杂质区域。

    Methods of fabricating non-volatile memory devices including double diffused junction regions
    60.
    发明授权
    Methods of fabricating non-volatile memory devices including double diffused junction regions 有权
    制造包括双扩散连接区域的非易失性存储器件的方法

    公开(公告)号：US08324052B2

    公开(公告)日：2012-12-04

    申请号：US13010583

    申请日：2011-01-20

    申请人： Dong-Yean Oh ,  Jai-Hyuk Song ,  Chang-Sub Lee ,  Chang-Hyun Lee ,  Hyun-Jae Kim

    发明人： Dong-Yean Oh ,  Jai-Hyuk Song ,  Chang-Sub Lee ,  Chang-Hyun Lee ,  Hyun-Jae Kim

    IPC分类号： H01L21/331

    CPC分类号： H01L27/11521 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11524

    摘要： A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between ones of the plurality of memory cell gates. Second impurity regions extend into the substrate to a second depth that is greater than the first depth between the string selection gate and a first one of the plurality of memory cell gates immediately adjacent thereto, and between the ground selection gate and a last one of the plurality of memory cell gates immediately adjacent thereto. Related fabrication methods are also discussed.

    摘要翻译： 非易失性存储器件包括半导体衬底上的串选择栅极和接地选择栅极，以及在串选择栅极和地选择栅极之间的衬底上的多个存储单元栅极。 第一杂质区域延伸到衬底中到多个存储单元门之间的第一深度。 第二杂质区域延伸到衬底中的第二深度，该第二深度大于串选择栅极与紧邻其之间的多个存储单元栅极中的第一深度之间以及在接地选择栅极和最后一个栅极选择栅极之间的第一深度 与其紧邻的多个存储单元门。 还讨论了相关的制造方法。