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51.发明申请Drain/source extension structure of a field effect transistor including doped high-k sidewall spacers 审中-公开包括掺杂的高k侧壁间隔物的场效应晶体管的漏极/源延伸结构公开(公告)号：US20050098818A1
公开(公告)日：2005-05-12
申请号：US11015061
申请日：2004-12-17
IPC分类号： H01L21/225 , H01L21/336 , H01L29/78 , H01L29/76
CPC分类号： H01L29/6659 , H01L21/2253 , H01L29/665 , H01L29/7833
摘要： High-k dielectric spacer elements on the gate electrode of a field effects transistor in combination with an extension region that is formed by dopant diffusion from the high-k spacer elements into the underlying semiconductor region provides for an increased charge carrier density in the extension region. In this way, the limitation of the charge carrier density to approximately the solid solubility of dopants in the extension region may be overcome, thereby allowing extremely shallow extension regions without unduly compromising the transistor performance.
摘要翻译： 场效应晶体管的栅极上的高k电介质隔离元件与由高k隔离元件掺入到下面的半导体区域中的掺杂剂扩散形成的延伸区组合提供了延伸区中增加的电荷载流子密度 。 以这种方式，可以克服电荷载流子密度近似于扩散区域中掺杂剂的固溶度的限制，从而允许非常浅的延伸区域而不会不利地损害晶体管的性能。
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52.发明申请Polysilicon line having a metal silicide region enabling linewidth scaling 有权具有能够进行线宽缩放的金属硅化物区域的多晶硅线公开(公告)号：US20050026379A1
公开(公告)日：2005-02-03
申请号：US10790974
申请日：2004-03-02
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L29/78
CPC分类号： H01L29/66507 , H01L21/28052 , H01L21/28518 , H01L29/66545 , H01L29/6656 , H01L29/7833
摘要： By maintaining the gate electrode covered during the process flow for forming metal silicide regions in the drain and source of a field effect transistor, an appropriate metal silicide may be formed on the gate electrode which meets the requirement for aggressive gate length scaling. Preferably, a nickel silicide is formed on the gate electrode, whereas the drain and source regions receive the well-established cobalt disilicide. Additionally, the gate electrode dopant profile is effectively decoupled from the drain and source dopant profile.
摘要翻译： 通过在场效应晶体管的漏极和源极中形成金属硅化物区域的工艺流程期间保持栅极电极被覆盖，可以在栅电极上形成适当的金属硅化物，以满足腐蚀性栅极长度缩放的要求。 优选地，在栅极电极上形成硅化镍，而漏极和源极区域接收良好建立的二硅化钴。 此外，栅极电极掺杂物分布与漏极和源极掺杂剂分布有效地解耦。
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53.发明授权Circuit element having a metal silicide region thermally stabilized by a barrier diffusion material 有权具有通过阻挡扩散材料热稳定的金属硅化物区域的电路元件公开(公告)号：US06838363B2
公开(公告)日：2005-01-04
申请号：US10402585
申请日：2003-03-28
IPC分类号： H01L21/265 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/425
CPC分类号： H01L29/66507 , H01L21/26506 , H01L21/28052 , H01L21/28518 , H01L29/665 , H01L29/6653
摘要： The introduction of a barrier diffusion material, such as nitrogen, into a silicon-containing conductive region, for example the drain and source regions and the gate electrode of a field effect transistor, allows the formation of nickel silicide, which is substantially thermally stable up to temperatures of 500° C. Thus, the device performance may significantly improve as the sheet resistance of nickel silicide is significantly less than that of nickel disilicide.
摘要翻译： 诸如氮的阻挡扩散材料引入含硅导电区域，例如场效应晶体管的漏极和源极区域和栅电极，允许形成基本上热稳定的硅化镍 到500℃的温度。因此，随着硅化镍的薄层电阻显着小于二硅化镍的薄膜电阻，器件性能可能显着提高。
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公开(公告)号：US06806153B2
公开(公告)日：2004-10-19
申请号：US10462893
申请日：2003-06-17
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2022 , H01L21/26506 , H01L21/26513
摘要： The present invention allows the manufacturing of field effect transistors with reduced thermal budget. A first amorphized region and a second amorphized region are formed in a substrate adjacent to the gate electrode by implanting ions of a non-doping element, the presence of which does not significantly alter the conductive properties of the substrate. The formation of the amorphized regions may be performed before or after the formation of a source region, a drain region, an extended source region and an extended drain region. The substrate is annealed to achieve solid phase epitaxial regrowth of the amorphized regions and to activate dopants in the source region, the drain region, the extended source region and the extended drain region.
摘要翻译： 本发明允许制造具有降低的热预算的场效应晶体管。 第一非晶化区域和第二非晶区域通过注入非掺杂元素的离子形成在与栅电极相邻的衬底中，其不存在不会显着地改变衬底的导电性能。 非晶化区域的形成可以在形成源极区域，漏极区域，扩展源极区域和延伸的漏极区域之前或之后进行。 将衬底退火以实现非晶化区域的固相外延再生长并激活源极区域，漏极区域，扩展源极区域和延伸漏极区域中的掺杂剂。
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55.发明授权Field effect transistor with reduced gate delay and method of fabricating the same 有权具有减小的栅极延迟的场效应晶体管及其制造方法公开(公告)号：US06798028B2
公开(公告)日：2004-09-28
申请号：US09847622
申请日：2001-05-02
IPC分类号： H01L2976
CPC分类号： H01L21/28052 , H01L21/28114 , H01L29/42376 , H01L29/4933
摘要： A transistor formed on a substrate comprises a gate electrode having a lateral extension at the foot of the gate electrode that is less than the average lateral extension of the gate electrode. The increased cross-section of the gate electrode compared to the rectangular cross-sectional shape of a prior art device provides for a significantly reduced gate resistance while the effective gate length, i.e., the lateral extension of the gate electrode at its foot, may be scaled down to a size of 100 nm and beyond. Moreover, a method for forming the field effect transistor described above is disclosed.
摘要翻译： 形成在基板上的晶体管包括栅电极，栅电极在栅极的脚处具有小于栅电极的平均横向延伸的横向延伸。 与现有技术的器件的矩形横截面形状相比，栅电极的横截面增加提供了显着降低的栅极电阻，而有效栅极长度，即栅电极在其脚处的横向延伸可以是 缩小到100nm以上的尺寸。 此外，公开了一种用于形成上述场效应晶体管的方法。
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公开(公告)号：US06703278B2
公开(公告)日：2004-03-09
申请号：US10208308
申请日：2002-07-30
IPC分类号： H01L21336
CPC分类号： H01L21/823462 , H01L21/28185 , H01L21/28194 , H01L21/31111 , H01L21/3144 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： A method of forming oxide layers of different thickness on a substrate is described, wherein the oxide layers preferably serve as gate insulation layers of field effect transistors. The method allows to form very thin, high quality oxide layers with a reduced number of masking steps compared to the conventional processing, wherein the thickness difference can be maintained within a range of some tenths of a nanometer. The method substantially eliminates any high temperature oxidations and is also compatible with most chemical vapor deposition techniques used for gate dielectric deposition in sophisticated semiconductor devices.
摘要翻译： 描述了在衬底上形成不同厚度的氧化物层的方法，其中氧化物层优选用作场效应晶体管的栅极绝缘层。 与常规处理相比，该方法允许形成具有减少数量的掩模步骤的非常薄的高质量氧化物层，其中厚度差可以保持在十分之几纳米的范围内。 该方法基本上消除了任何高温氧化，并且也与用于复杂半导体器件中的栅极介电沉积的大多数化学气相沉积技术相兼容。
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57.发明授权Method of monitoring the temperature of a rapid thermal anneal process in semiconductor manufacturing and a test wafer for use in this method 失效监测半导体制造中的快速热退火工艺的温度的方法和用于该方法的测试晶片公开(公告)号：US06436724B1
公开(公告)日：2002-08-20
申请号：US09808391
申请日：2001-03-14
IPC分类号： H01L2166
CPC分类号： H01L22/12
摘要： A method of monitoring the temperature of a rapid thermal annealing (RTA) process and a test wafer for use in this process are disclosed. The method includes the step of forming a distorted surface region in a crystalline semiconductor wafer and the mounting of the wafer in a process chamber for performing the RTA process in a reaction gas containing ambient. The distorted surface region of the semiconductor wafer enables higher diffusion rates of reaction gas components into the wafer surface and therefore a higher growth rate of a reaction product film. The increase of the reaction product film thickness enables an increase of the film thickness measurement accuracy and thus the accuracy in determining the RTA temperature homogeneity. In one embodiment, a distorted surface region in a crystalline silicon test wafer is produced by implanting ions at low doses into a wafer substrate up to a pre-amorphization level of the surface crystalline lattice. As a low dose of heavy ions is sufficient for producing the distorted surface region, the test wafers are produced at low costs. Additionally, a method of reworking test wafers that have been used in an RTA monitoring method is presented. By reworking the test wafers and preparing for the next RTA-monitoring the wafer costs can be efficiently reduced.
摘要翻译： 公开了一种监测快速热退火（RTA）工艺的温度和用于该工艺的测试晶片的方法。 该方法包括在晶体半导体晶片中形成失真的表面区域以及将晶片安装在用于在含有环境的反应气体中进行RTA处理的处理室中的步骤。 半导体晶片的变形的表面区域能够使反应气体成分进入晶片表面的扩散速率更高，因此反应产物膜的生长速度更高。 反应产物膜厚度的增加能够提高膜厚测量精度，从而能够提高测定RTA温度均匀性的精度。 在一个实施例中，晶体硅测试晶片中的失真的表面区域是通过将低剂量的离子注入到晶片衬底中而产生的，直到表面晶格的非晶化阶段为止。 由于低剂量的重离子足以产生变形的表面区域，所以以低成本生产测试晶片。 另外，提出了一种在RTA监控方法中使用的重做测试晶片的方法。 通过重新测试晶片并准备下一个RTA监控，可以有效降低晶圆成本。
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公开(公告)号：US06410410B1
公开(公告)日：2002-06-25
申请号：US09852535
申请日：2001-05-10
IPC分类号： H01L21225
CPC分类号： H01L29/6659 , H01L21/2255 , H01L29/42368 , H01L29/7833
摘要： A method is disclosed in which a lightly doped region in a semiconductor layer is obtained by diffusing dopant atoms of a first and second type into the underlying semiconductor layer. Preferably, the method is applied to the formation of lightly doped source and drain regions in a field effect transistor so as to obtain a required gradual dopant concentration transition from the general region to the drain and source regions for avoiding the hot carrier effect. Advantageously, a diffusion of the dopant atoms is initiated during an oxidizing step in which the thickness of the gate insulation layer is increased at the edge portions thereof.
摘要翻译： 公开了一种通过将第一和第二类型的掺杂剂原子扩散到下面的半导体层中而获得半导体层中的轻掺杂区域的方法。 优选地，该方法被应用于在场效应晶体管中形成轻掺杂的源极和漏极区域，以便获得从一般区域到漏极和源极区域所需的逐渐掺杂剂浓度跃迁，以避免热载流子效应。 有利地，掺杂剂原子的扩散在其栅极绝缘层的厚度在其边缘部分增加的氧化步骤期间开始。
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59.发明授权Collimated deposition of titanium onto a substantially vertical nitride spacer sidewall to prevent silicide bridging 失效准直的钛沉积在基本垂直的氮化物间隔壁侧壁上以防止硅化物桥接
公开(公告)号：US6121138A
公开(公告)日：2000-09-19
申请号：US69014
申请日：1998-04-28
申请人： Karsten Wieczorek , Fred N. Hause
发明人： Karsten Wieczorek , Fred N. Hause
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/336 , H01L21/44
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28518 , H01L21/32051
摘要： An integrated circuit fabrication process and transistor is provided in which salicidation is virtually eliminated from the spacer sidewall surface. Absent salicidation on that surface, bridging effects cannot occur regardless of the anneal conditions. The spacer sidewall surfaces is made substantially perpendicular to the substrate upper surface such that when a refractory metal is subsequently deposited on the semiconductor topography, the refractory metal will not accumulate on that perpendicular surface. The spacer is deposited from a specifically designed plasma enhanced chemical vapor deposition process to maintain the spacer sidewall surfaces commensurate with the gate conductor sidewall surfaces. The refractory metal is directionally deposited so that little if any metal will form on vertical surfaces and substantially all of the metal will deposit on horizontal surfaces.
摘要翻译： 提供了一种集成电路制造工艺和晶体管，其中实际上从间隔壁侧壁表面消除了氧化作用。 无论退火条件如何，桥接效应都不会发生在表面上。 隔离件侧壁表面基本上垂直于基板上表面，使得当难熔金属随后沉积在半导体形貌上时，难熔金属将不会积聚在该垂直表面上。 间隔物由专门设计的等离子体增强化学气相沉积工艺沉积，以保持隔板侧壁表面与栅极导体侧壁表面相当。 难熔金属被定向沉积，使得在垂直表面上几乎没有金属形成，并且基本上所有的金属将沉积在水平表面上。
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60.发明授权Etch stop layer of reduced thickness for patterning a dielectric material in a contact level of closely spaced transistors 有权用于图案化紧密间隔晶体管的接触电平的介电材料的减小厚度的蚀刻停止层公开(公告)号：US08097542B2
公开(公告)日：2012-01-17
申请号：US12260147
申请日：2008-10-29
IPC分类号： H01L21/31
CPC分类号： H01L21/76826 , H01L21/76832 , H01L21/823412 , H01L21/823425 , H01L21/823807 , H01L29/7843 , Y02P80/30
摘要： In a dual stress liner approach, an intermediate etch stop material may be provided on the basis of a plasma-assisted oxidation process rather than by deposition so the corresponding thickness of the etch stop material may be reduced. Consequently, the resulting aspect ratio may be less pronounced compared to conventional strategies, thereby reducing deposition-related irregularities which may translate into a significant reduction of yield loss, in particular for highly scaled semiconductor devices.
摘要翻译： 在双重应力衬垫方法中，可以基于等离子体辅助氧化工艺而不是通过沉积来提供中间蚀刻停止材料，从而减小蚀刻停止材料的对应厚度。 因此，与常规策略相比，所产生的纵横比可能不太明显，从而减少沉积相关的不规则性，这可能转化为产量损失的显着降低，特别是对于高度缩放的半导体器件。
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