公开(公告)号：US07952392B2

公开(公告)日：2011-05-31

申请号：US12605607

申请日：2009-10-26

申请人： Jun Koyama ,  Kengo Akimoto ,  Masashi Tsubuku

发明人： Jun Koyama ,  Kengo Akimoto ,  Masashi Tsubuku

IPC分类号： H03K19/20 ,  H03K19/094

CPC分类号： H03K19/094 ,  H01L27/0883 ,  H01L27/1225 ,  H03K19/09407 ,  H03K19/09421 ,  H03K19/096

摘要： An object is to apply a transistor using an oxide semiconductor to a logic circuit including an enhancement transistor. The logic circuit includes a depletion transistor 101 and an enhancement transistor 102. The transistors 101 and 102 each include a gate electrode, a gate insulating layer, a first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode, and a drain electrode. The transistor 102 includes a reduction prevention layer provided over a region in the first oxide semiconductor layer between the source electrode and the drain electrode.

摘要翻译： 目的是将使用氧化物半导体的晶体管施加到包括增强晶体管的逻辑电路。 逻辑电路包括耗尽晶体管101和增强晶体管102.晶体管101和102各自包括栅电极，栅极绝缘层，第一氧化物半导体层，第二氧化物半导体层，源电极和漏电极 。 晶体管102包括在源电极和漏极之间的第一氧化物半导体层中的区域上设置的还原防止层。

公开(公告)号：US07948040B2

公开(公告)日：2011-05-24

申请号：US12031893

申请日：2008-02-15

申请人： Shunpei Yamazaki ,  Kengo Akimoto

发明人： Shunpei Yamazaki ,  Kengo Akimoto

IPC分类号： H01L29/78 ,  H01L29/786

CPC分类号： H01L29/78621 ,  H01L27/12 ,  H01L27/1248 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/66757 ,  H01L2029/7863

摘要： A semiconductor device includes a semiconductor layer overlapping with a gate electrode and having an impurity region outside a region which overlaps with the gate electrode; a first conductive layer which is provided on a side provided with the gate electrode of the semiconductor layer and partially in contact with the impurity region; an insulating layer provided over the gate electrode and the first conductive layer; and a second conductive layer which is formed in the insulating layer and in contact with the first conductive layer through an opening at least part of which overlaps with the first conductive layer.

摘要翻译： 半导体器件包括与栅电极重叠并且在与栅电极重叠的区域之外具有杂质区域的半导体层; 第一导电层，其设置在设置有半导体层的栅电极并且部分地与杂质区接触的一侧; 设置在所述栅电极和所述第一导电层上的绝缘层; 以及第二导电层，其形成在所述绝缘层中并且通过其至少一部分与所述第一导电层重叠的开口与所述第一导电层接触。

公开(公告)号：US20110084269A1

公开(公告)日：2011-04-14

申请号：US12899265

申请日：2010-10-06

申请人： Shunpei Yamazaki ,  Suzunosuke Hiraishi ,  Kengo Akimoto ,  Junichiro Sakata

发明人： Shunpei Yamazaki ,  Suzunosuke Hiraishi ,  Kengo Akimoto ,  Junichiro Sakata

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/7869 ,  H01L27/1225 ,  H01L29/45

摘要： An object is to reduce contact resistance between an oxide semiconductor layer and source and drain electrode layers electrically connected to the oxide semiconductor layer in a thin film transistor including the oxide semiconductor layer. The source and drain electrode layers have a stacked structure of two or more layers. In this stack of layers, a layer in contact with the oxide semiconductor layer is a thin indium layer or a thin indium-alloy layer. Note that the oxide semiconductor layer contains indium. A second layer or second and any of subsequent layers in the source and drain electrode layers are formed using an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, an alloy containing any of these elements as a component, an alloy containing any of these elements in combination, or the like.

摘要翻译： 本发明的目的是减少在包括氧化物半导体层的薄膜晶体管中氧化物半导体层与与氧化物半导体层电连接的源极和漏极电极层之间的接触电阻。 源极和漏极电极层具有两层或更多层的堆叠结构。 在该堆叠层中，与氧化物半导体层接触的层是薄的铟层或薄的铟 - 合金层。 注意，氧化物半导体层含有铟。 使用选自Al，Cr，Cu，Ta，Ti，Mo和W的元素来形成源极和漏极电极层中的第二层或第二层以及后续层中的任何一层，包含任何这些元素作为组分的合金， 合并这些元素中的任何一种的合金等。

公开(公告)号：US07923356B2

公开(公告)日：2011-04-12

申请号：US11295470

申请日：2005-12-07

申请人： Toru Takayama ,  Kengo Akimoto

发明人： Toru Takayama ,  Kengo Akimoto

IPC分类号： H01L21/00

CPC分类号： H01L29/66757 ,  H01L29/78666 ,  H01L29/78675

摘要： Concerning an art related to a manufacturing method for a semiconductor device having an integrated circuit using thin film transistors on a substrate, a problem is to provide a condition for forming an amorphous silicon film having distortion. In the deposition of an amorphous silicon film using a sputter method, a condition is provided with a frequency of 15 to 25 kHz and a deposition power of 0.5 to 3 kW. This can sufficiently contain Ar at 10×1020/cm3 or more in an amorphous silicon film, thus making possible to form an amorphous silicon film having distortion.

摘要翻译： 关于具有在基板上使用薄膜晶体管的集成电路的半导体器件的制造方法的技术，存在的问题是提供一种形成具有变形的非晶硅膜的条件。 在使用溅射法沉积非晶硅膜的情况下，提供15至25kHz的频率和0.5至3kw的沉积功率的条件。 这可以在非晶硅膜中充分地含有10×10 20 / cm 3以上的Ar，因此能够形成具有变形的非晶硅膜。

公开(公告)号：US07910490B2

公开(公告)日：2011-03-22

申请号：US12432403

申请日：2009-04-29

申请人： Kengo Akimoto ,  Tatsuya Honda ,  Norihito Sone

发明人： Kengo Akimoto ,  Tatsuya Honda ,  Norihito Sone

IPC分类号： H01L21/461 ,  H01L21/302

CPC分类号： H01L29/78696 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/428 ,  H01L21/465 ,  H01L21/477 ,  H01L27/1225 ,  H01L27/1285 ,  H01L29/04 ,  H01L29/045 ,  H01L29/7869

摘要： An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

公开(公告)号：US20100072470A1

公开(公告)日：2010-03-25

申请号：US12556695

申请日：2009-09-10

申请人： Shunpei Yamazaki ,  Kengo Akimoto ,  Shigeki Komori ,  Hideki Uochi ,  Tomoya Futamura ,  Takahiro Kasahara

发明人： Shunpei Yamazaki ,  Kengo Akimoto ,  Shigeki Komori ,  Hideki Uochi ,  Tomoya Futamura ,  Takahiro Kasahara

IPC分类号： H01L33/00

CPC分类号： H01L29/7869 ,  H01L27/0266 ,  H01L27/1225 ,  H01L27/124

摘要： A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, a channel protective layer overlapping with a channel formation region of the first oxide semiconductor layer, and a pair of a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the channel protective layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.

摘要翻译： 保护电路包括非线性元件，其包括栅电极，覆盖栅电极的栅极绝缘层，与栅绝缘层上的栅电极重叠的第一氧化物半导体层，与沟道形成区重叠的沟道保护层 的第一氧化物半导体层，以及一对第一布线层和第二布线层，其端部与沟道保护层上的栅电极重叠，并且其中层叠有导电层和第二氧化物半导体层。 在栅极绝缘层上，具有不同性质的氧化物半导体层彼此结合，由此可以进行与肖特基结的稳定操作。 因此，可以降低结漏电，提高非线性元件的特性。

公开(公告)号：US07541213B2

公开(公告)日：2009-06-02

申请号：US11822924

申请日：2007-07-11

申请人： Kengo Akimoto

发明人： Kengo Akimoto

IPC分类号： H01L21/00

CPC分类号： H01L27/12 ,  H01L27/105 ,  H01L27/11293 ,  H01L27/1214 ,  H01L27/1266

摘要： The semiconductor device includes a thin film transistor; a first interlayer insulating film over the thin film transistor; a first electrode electrically connected to one of a source region and a drain region, over the first interlayer insulating film; a second electrode electrically connected to the other of the source region and the drain region; a second interlayer insulating film formed over the first interlayer insulating film, the first electrode, and the second electrode; a first wiring electrically connected to one of the first electrode and the second electrode, on the second interlayer insulating film; and a second wiring not electrically connected to the other of the first electrode and the second electrode, on the second interlayer insulating film; in which the second wiring is not electrically connected to the other of the first electrode and the second electrode by a separation region formed in the second interlayer insulating film.

摘要翻译： 半导体器件包括薄膜晶体管; 薄膜晶体管上的第一层间绝缘膜; 在所述第一层间绝缘膜上方电连接到源区和漏区之一的第一电极; 电源地连接到所述源极区域和所述漏极区域中的另一个的第二电极; 形成在第一层间绝缘膜，第一电极和第二电极上的第二层间绝缘膜; 在第二层间绝缘膜上电连接到第一电极和第二电极之一的第一布线; 以及在所述第二层间绝缘膜上不与所述第一电极和所述第二电极中的另一个电连接的第二布线; 其中第二布线不通过形成在第二层间绝缘膜中的分离区域而电连接到第一电极和第二电极中的另一个。

公开(公告)号：US07538238B2

公开(公告)日：2009-05-26

申请号：US10482373

申请日：2002-07-02

申请人： Kengo Akimoto ,  Motoo Sumida ,  Kenichi Higashiyama ,  Shigeaki Fujikawa

发明人： Kengo Akimoto ,  Motoo Sumida ,  Kenichi Higashiyama ,  Shigeaki Fujikawa

IPC分类号： A23D9/00

CPC分类号： C12P7/6472 ,  A23C9/1528 ,  A23C11/04 ,  A23K20/158 ,  A23L33/115 ,  A23L33/12 ,  C11C3/08 ,  C11C3/10

摘要： The present invention relates to a production method of an oil containing triglyceride in which medium chain fatty acids are bound to the 1- and 3-positions of the triglyceride and polyunsaturated fatty acid is bound to the 2 position by allowing lipase, which specifically acts on ester bonds at the 1- and 3-positions that has been immobilized on a porous ion exchange resin support having a pore size of about 100 Angstroms or more, to act on a mixture of medium-chain fatty acids and raw material oil containing at least one polyunsaturated fatty acid selected from the group consisting of ω6 series polyunsaturated fatty acid having 18 or more carbon atoms and 3 or more double bonds and ω9 series polyunsaturated fatty acid having 18 or more carbon atoms and 2 or more double bonds, but not containing ω3 series polyunsaturated fatty acid, oils and fats or triglycerides obtained by that method, and the use of the oils and fats or triglycerides in a food, beverage or pharmaceutical composition.

摘要翻译： 本发明涉及含有甘油三酯的油的制备方法，其中中链脂肪酸与甘油三酯的1位和3位结合，多不饱和脂肪酸通过使脂肪酶特异性地作用于2位而结合到2位上 在固定在孔径为约100埃以上的多孔离子交换树脂载体上的1-位和3-位的酯键作用于中链脂肪酸和至少含有至少 一种选自具有18个或更多个碳原子的ω-6系多不饱和脂肪酸和3个或更多个双键的多不饱和脂肪酸和具有18个或更多个碳原子和2个或更多个双键但不含ω3的ω-系列多不饱和脂肪酸 系列多不饱和脂肪酸，通过该方法获得的油和脂肪或甘油三酯，以及在食品，饮料或药物中使用油和脂肪或甘油三酸酯 l组成。

公开(公告)号：US07492090B2

公开(公告)日：2009-02-17

申请号：US10937904

申请日：2004-09-10

申请人： Shunpei Yamazaki ,  Toru Takayama ,  Naoya Sakamoto ,  Kengo Akimoto ,  Keiji Sato ,  Tetsunori Maruyama

发明人： Shunpei Yamazaki ,  Toru Takayama ,  Naoya Sakamoto ,  Kengo Akimoto ,  Keiji Sato ,  Tetsunori Maruyama

IPC分类号： H01J63/04 ,  H01J1/62 ,  H05B33/04

CPC分类号： H01L51/5206 ,  H01L27/3244 ,  H01L27/3246 ,  H01L27/3281 ,  H01L27/3295 ,  H01L51/5215 ,  Y10S428/917

摘要： According to one aspect of the present invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide is applied as an electrode on the side of injecting a hole (a hole injection electrode; an anode) instead of the conventional conductive transparent oxide layer such as ITO. In addition, according to another aspect of the invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide, each of which content is different, is applied as a hole injection electrode. Preferably, silicon or a silicon oxide concentration of the conductive layer on the side where it is connected to a TFT ranges from 1 atomic % to 6 atomic % and a silicon or silicon oxide concentration on the side of a layer containing an organic compound ranges from 7 atomic % to 15 atomic %.

摘要翻译： 根据本发明的一个方面，在注入孔（空穴注入电极，阳极）的一侧，代替传统的导电透明氧化物，涂覆含有硅或氧化硅的导电透明氧化物层的叠层结构作为电极 层如ITO。 此外，根据本发明的另一方面，作为空穴注入电极，施加含有硅或氧化硅的导电性透明氧化物层（其含量不同）的叠层结构。 优选地，在与TFT连接的一侧上的导电层的硅或氧化硅浓度范围为1原子％至6原子％，并且在含有机化合物的层侧的硅或氧化硅浓度范围为 7原子％至15原子％。

公开(公告)号：US20090042326A1

公开(公告)日：2009-02-12

申请号：US12239248

申请日：2008-09-26

申请人： Shunpei Yamazaki ,  Toru Takayama ,  Naoya Sakamoto ,  Kengo Akimoto ,  Keiji Sato ,  Tetsunori Maruyama

发明人： Shunpei Yamazaki ,  Toru Takayama ,  Naoya Sakamoto ,  Kengo Akimoto ,  Keiji Sato ,  Tetsunori Maruyama

IPC分类号： H01L33/00

CPC分类号： H01L51/5206 ,  H01L27/3244 ,  H01L27/3246 ,  H01L27/3281 ,  H01L27/3295 ,  H01L51/5215 ,  Y10S428/917

摘要： According to one aspect of the present invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide is applied as an electrode on the side of injecting a hole (a hole injection electrode; an anode) instead of the conventional conductive transparent oxide layer such as ITO. In addition, according to another aspect of the invention, a laminated structure of conductive transparent oxide layers containing silicon or silicon oxide, each of which content is different, is applied as a hole injection electrode. Preferably, silicon or a silicon oxide concentration of the conductive layer on the side where it is connected to a TFT ranges from 1 atomic % to 6 atomic % and a silicon or silicon oxide concentration on the side of a layer containing an organic compound ranges from 7 atomic % to 15 atomic %.

摘要翻译： 根据本发明的一个方面，在注入孔（空穴注入电极，阳极）的一侧，代替传统的导电透明氧化物，涂覆含有硅或氧化硅的导电透明氧化物层的叠层结构作为电极 层如ITO。 此外，根据本发明的另一方面，作为空穴注入电极，施加含有硅或氧化硅的导电性透明氧化物层（其含量不同）的叠层结构。 优选地，在与TFT连接的一侧上的导电层的硅或氧化硅浓度范围为1原子％至6原子％，并且在含有机化合物的层侧的硅或氧化硅浓度范围为 7原子％至15原子％。