公开(公告)号：US07622218B2

公开(公告)日：2009-11-24

申请号：US11398700

申请日：2006-04-06

申请人： Kozo Watanabe ,  Masao Fukunaga ,  Ichiro Yasuoka ,  Toshiro Kume

发明人： Kozo Watanabe ,  Masao Fukunaga ,  Ichiro Yasuoka ,  Toshiro Kume

IPC分类号： H01M4/64 ,  H01M10/24

CPC分类号： H01M10/0587 ,  H01M4/0404 ,  H01M4/139 ,  H01M10/052 ,  Y10T29/10 ,  Y10T29/49108 ,  Y10T29/4911 ,  Y10T29/49112 ,  Y10T29/49114 ,  Y10T29/49115

摘要： An electrode in sheet form includes a current collector and an electrode mixture layer carried on each side thereof. The electrode is bent in the longitudinal direction thereof, to cause a large number of cracks in at least the electrode mixture layer to be positioned on the inner side of the current collector when wound, such that the cracks extend from the surface of the electrode mixture layer to the current collector in the direction intersecting with the longitudinal direction of the electrode. This bending process includes the steps of: bending the electrode at a curvature that is smaller than that of the winding core at least once; and thereafter bending the electrode at a curvature that is equal to or larger than that of the winding core. For example, this process is performed by arranging rollers such that their diameters decrease gradually and pressing the electrode against these rollers. This invention provides an electrode that does not break when wound to form an electrode assembly.

摘要翻译： 片状电极包括集电体和在其每一侧承载的电极混合物层。 电极沿其长度方向弯曲，至少在电极混合物层中产生大量的裂纹，当缠绕时将其定位在集电体的内侧，使得裂纹从电极混合物的表面延伸 在与电极的纵向相交的方向上与集电体层叠。 该弯曲过程包括以下步骤：将电极弯曲至少小于绕组芯的曲率; 然后以等于或大于卷芯的曲率弯曲电极。 例如，该方法通过布置辊子来实现，使得它们的直径逐渐减小并且将电极压靠在这些辊子上。 本发明提供一种当缠绕形成电极组件时不破裂的电极。

公开(公告)号：US20070246780A1

公开(公告)日：2007-10-25

申请号：US11723344

申请日：2007-03-19

申请人： Kozo Watanabe ,  Shoji Yoshida ,  Masashi Sahara ,  Shinichi Tanabe ,  Takashi Hashimoto

发明人： Kozo Watanabe ,  Shoji Yoshida ,  Masashi Sahara ,  Shinichi Tanabe ,  Takashi Hashimoto

IPC分类号： H01L29/94 ,  H01L21/8234

CPC分类号： H01L29/872 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/7833

摘要： A technology is provided where a high performance Schottky-barrier diode and other semiconductor elements can be formed in the same chip controlling the increase in the number of steps. After a silicon oxide film is deposited over a substrate where an n-channel type MISFET is formed and the silicon oxide film over a gate electrode and n+ type semiconductor region is selectively removed, a Co film is deposited over the substrate and a CoSi2 layer is formed over the n+ type semiconductor region and the gate electrode by applying a heat treatment to the substrate. After a silicon nitride film is deposited over the substrate and an aperture reaching the substrate is formed by removing the silicon nitride-film and the silicon oxide film at the anode formation part of the Schottky barrier diode, a Ti film is deposited over the substrate including the inside of the aperture, and a TiSi2 layer which becomes an anode electrode of the Schottky-barrier diode is formed at the bottom of the aperture by applying a heat treatment to the substrate.

摘要翻译： 提供了一种技术，其中可以在同一芯片中形成高性能肖特基势垒二极管和其他半导体元件，以控制步骤数量的增加。 在氧化硅膜沉积在其上形成n沟道型MISFET的衬底上并且选择性地去除栅电极和n + +型半导体区之上的氧化硅膜之后，沉积Co膜 并且通过对衬底进行热处理，在n + +型半导体区域和栅极上形成CoSi 2 +层。 在氮化硅膜沉积在衬底之上并且通过去除肖特基势垒二极管的阳极形成部分处的氮化硅膜和氧化硅膜来形成到达衬底的孔，在衬底上沉积Ti膜，包括 通过对基板进行热处理，在孔的底部形成孔径的内部和成为肖特基势垒二极管的阳极的TiSi 2层。

公开(公告)号：US5631182A

公开(公告)日：1997-05-20

申请号：US327861

申请日：1994-10-18

申请人： Naokatsu Suwanai ,  Hiroyuki Miyazawa ,  Atushi Ogishima ,  Masaki Nagao ,  Kyoichiro Asayama ,  Hiroyuki Uchiyama ,  Yoshiyuki Kaneko ,  Takashi Yoneoka ,  Kozo Watanabe ,  Kazuya Endo ,  Hiroki Soeda

发明人： Naokatsu Suwanai ,  Hiroyuki Miyazawa ,  Atushi Ogishima ,  Masaki Nagao ,  Kyoichiro Asayama ,  Hiroyuki Uchiyama ,  Yoshiyuki Kaneko ,  Takashi Yoneoka ,  Kozo Watanabe ,  Kazuya Endo ,  Hiroki Soeda

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10844 ,  H01L27/10805 ,  H01L27/10808

摘要： In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region as a memory cell array region a first MISFET having a gate electrode and source and drain regions; first and second capacity electrodes and a dielectric film extending onto a first insulating film on the gate electrode; a second insulating film positioned on the second capacity electrode; and a first wiring positioned on the second insulating film, while in a second region as a peripheral circuit region there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a third insulating film on the first insulating film; a second insulating film on the third insulating film; and a second wiring on the second insulating film.

摘要翻译： 在其中每个存储单元由存储单元选择MISFET的串联电路和层叠结构的信息存储电容器构成的半导体存储器电路器件中，在第一区域中存在作为存储单元阵列区域的第一MISFET，其具有 栅极电极和源极和漏极区域; 第一和第二电容电极和延伸到栅电极上的第一绝缘膜上的电介质膜; 位于所述第二容量电极上的第二绝缘膜; 以及位于所述第二绝缘膜上的第一布线，而在作为外围电路区域的第二区域中存在具有栅极电极和源极和漏极区域的第二MISFET; 栅电极上的第一绝缘膜; 第一绝缘膜上的第三绝缘膜; 第三绝缘膜上的第二绝缘膜; 以及在第二绝缘膜上的第二布线。

公开(公告)号：US4761980A

公开(公告)日：1988-08-09

申请号：US835027

申请日：1986-02-28

申请人： Yoshio Kawashima ,  Shunji Ogata ,  Masaaki Yokoyama ,  Masato Tomiku ,  Tsuneo Yamada ,  Tsutomu Kuno ,  Hisao Murakami ,  Hiroyuki Morimoto ,  Toyoshige Myojo ,  Kozo Watanabe ,  Toshihiro Tanaka

发明人： Yoshio Kawashima ,  Shunji Ogata ,  Masaaki Yokoyama ,  Masato Tomiku ,  Tsuneo Yamada ,  Tsutomu Kuno ,  Hisao Murakami ,  Hiroyuki Morimoto ,  Toyoshige Myojo ,  Kozo Watanabe ,  Toshihiro Tanaka

IPC分类号： B21D43/02 ,  B21D43/09 ,  B21D43/28 ,  B21K27/02 ,  B23D33/00 ,  B21J7/46 ,  B21J1/06

CPC分类号： B23D33/006 ,  B21D43/021 ,  B21D43/09 ,  B21D43/285 ,  B21K27/02 ,  Y10T83/041 ,  Y10T83/283

摘要： Disclosed is a method and apparatus for feeding a material to a hot forging machine in a forging line in which a coiled material is uncoiled, straightened, fed intermittently by pinch rollers through a heating device, cut by a cutting device and then fed into a hot forging machine. The method has the steps of preparing a driving device which drives the pinch rollers mechanically independently from the hot forging machine; picking up the timing of forging conducted by the hot forging machine as an electric signal, and controlling the driving device in accordance with the electric signal.

摘要翻译： 公开了一种在锻造线中向热锻造机供给材料的方法和装置，其中卷绕材料被卷起，拉直，通过夹送辊通过加热装置间歇地进给，由切割装置切割，然后被送入热 锻造机。 该方法具有以下步骤：制备驱动装置，其与热锻机器机械地独立地驱动夹送辊; 拾取由热锻造机进行锻造的时刻作为电信号，并根据电信号控制驱动装置。

公开(公告)号：US08179650B2

公开(公告)日：2012-05-15

申请号：US12119237

申请日：2008-05-12

申请人： Kozo Watanabe ,  Hajime Nishino ,  Kazuya Maegawa

发明人： Kozo Watanabe ,  Hajime Nishino ,  Kazuya Maegawa

IPC分类号： H02H9/02

CPC分类号： H01M10/482 ,  H01M10/0525 ,  Y10T307/735

摘要： A power supply apparatus includes: a plurality of batteries; a changeover portion switching the connection between the plurality of batteries; a short-circuit battery detection portion, if an internal short-circuit is produced in any of the plurality of batteries, detecting this internal short-circuit battery; and a changeover control portion, if the short-circuit battery detection portion detects the internal short-circuit battery, allowing the changeover portion to switch the connection between the plurality of batteries in such a way that this internal short-circuit battery and at least one of the other batteries are connected in series to thereby form a closed circuit.

摘要翻译： 电源装置包括：多个电池; 切换部，切换所述多个电池之间的连接; 短路电池检测部，如果在所述多个电池中的任一个中产生内部短路，则检测该内部短路电池; 以及切换控制部，如果短路电池检测部检测到内部短路电池，则允许切换部以这样的方式切换多个电池之间的连接，使得该内部短路电池和至少一个 的其他电池串联连接，从而形成闭合电路。

公开(公告)号：US07750427B2

公开(公告)日：2010-07-06

申请号：US12349348

申请日：2009-01-06

申请人： Kozo Watanabe ,  Shoji Yoshida ,  Masashi Sahara ,  Shinichi Tanabe ,  Takashi Hashimoto

发明人： Kozo Watanabe ,  Shoji Yoshida ,  Masashi Sahara ,  Shinichi Tanabe ,  Takashi Hashimoto

IPC分类号： H01L27/095

CPC分类号： H01L29/872 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/7833

摘要： A technology is provided where a high performance Schottky-barrier diode and other semiconductor elements can be formed in the same chip controlling the increase in the number of steps. After a silicon oxide film is deposited over a substrate where an n-channel type MISFET is formed and the silicon oxide film over a gate electrode and n+ type semiconductor region is selectively removed, a Co film is deposited over the substrate and a CoSi2 layer is formed over the n+ type semiconductor region and the gate electrode by applying a heat treatment to the substrate. After a silicon nitride film is deposited over the substrate and an aperture reaching the substrate is formed by removing the silicon nitride film and the silicon oxide film at the anode formation part of the Schottky barrier diode, a Ti film is deposited over the substrate including the inside of the aperture, and a TiSi2 layer which becomes an anode electrode of the Schottky-barrier diode is formed at the bottom of the aperture by applying a heat treatment to the substrate.

摘要翻译： 提供了一种技术，其中可以在同一芯片中形成高性能肖特基势垒二极管和其他半导体元件，以控制步骤数量的增加。 在氧化硅膜沉积在其上形成n沟道型MISFET的衬底上并且选择性地去除栅电极和n +型半导体区上的氧化硅膜之后，在衬底上沉积Co膜，并且CoSi 2层是 通过对基板进行热处理而形成在n +型半导体区域和栅电极之上。 在氮化硅膜沉积在衬底上之后，通过去除肖特基势垒二极管的阳极形成部分处的氮化硅膜和氧化硅膜来形成到达衬底的孔径，在衬底上沉积Ti膜 在孔的内侧，通过对基板进行热处理，在孔的底部形成成为肖特基势垒二极管的阳极的TiSi 2层。

公开(公告)号：US07504297B2

公开(公告)日：2009-03-17

申请号：US11723344

申请日：2007-03-19

申请人： Kozo Watanabe ,  Shoji Yoshida ,  Masashi Sahara ,  Shinichi Tanabe ,  Takashi Hashimoto

发明人： Kozo Watanabe ,  Shoji Yoshida ,  Masashi Sahara ,  Shinichi Tanabe ,  Takashi Hashimoto

IPC分类号： H01L21/8234

CPC分类号： H01L29/872 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/7833

摘要： A technology is provided where a high performance Schottky-barrier diode and other semiconductor elements can be formed in the same chip controlling the increase in the number of steps. After a silicon oxide film is deposited over a substrate where an n-channel type MISFET is formed and the silicon oxide film over a gate electrode and n+ type semiconductor region is selectively removed, a Co film is deposited over the substrate and a CoSi2 layer is formed over the n+ type semiconductor region and the gate electrode by applying a heat treatment to the substrate. After a silicon nitride film is deposited over the substrate and an aperture reaching the substrate is formed by removing the silicon nitride film and the silicon oxide film at the anode formation part of the Schottky barrier diode, a Ti film is deposited over the substrate including the inside of the aperture, and a TiSi2 layer which becomes an anode electrode of the Schottky-barrier diode is formed at the bottom of the aperture by applying a heat treatment to the substrate.

摘要翻译： 提供了一种技术，其中可以在同一芯片中形成高性能肖特基势垒二极管和其他半导体元件，以控制步骤数量的增加。 在氧化硅膜沉积在其上形成n沟道型MISFET的衬底上并且选择性地去除栅电极和n +型半导体区上的氧化硅膜之后，在衬底上沉积Co膜，并且CoSi 2层是 通过对基板进行热处理而形成在n +型半导体区域和栅电极之上。 在氮化硅膜沉积在衬底上之后，通过去除肖特基势垒二极管的阳极形成部分处的氮化硅膜和氧化硅膜来形成到达衬底的孔径，在衬底上沉积Ti膜 在孔的内侧，通过对基板进行热处理，在孔的底部形成成为肖特基势垒二极管的阳极的TiSi 2层。

公开(公告)号：US07397104B2

公开(公告)日：2008-07-08

申请号：US10778081

申请日：2004-02-17

申请人： Norio Suzuki ,  Hiroyuki Ichizoe ,  Masayuki Kojima ,  Keiji Okamoto ,  Shinichi Horibe ,  Kozo Watanabe ,  Yasuko Yoshida ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Ishitsuka ,  Atsushi Ogishima ,  Maki Shimoda

发明人： Norio Suzuki ,  Hiroyuki Ichizoe ,  Masayuki Kojima ,  Keiji Okamoto ,  Shinichi Horibe ,  Kozo Watanabe ,  Yasuko Yoshida ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Ishitsuka ,  Atsushi Ogishima ,  Maki Shimoda

IPC分类号： H01L21/00

CPC分类号： H01L21/76229 ,  H01L21/76224 ,  H01L21/76232 ,  H01L27/10852 ,  H01L28/91

摘要： A semiconductor integrated circuit device is provided which includes an active region, a shallow groove isolation adjacent to the active region, and a semiconductor element formed in the active region and having a gate. The sum of a width of the active region and a width of the shallow groove isolation constitutes a minimum pitch in the direction of a gate width of the gate, and the width of the active region is set larger than one-half of the minimum pitch.

摘要翻译： 提供一种半导体集成电路器件，其包括有源区，与有源区相邻的浅槽隔离，以及形成在有源区中并具有栅极的半导体元件。 有源区的宽度和浅槽隔离的宽度的和构成栅极的栅极宽度方向上的最小间距，并且有源区的宽度被设定为大于最小间距的一半 。

公开(公告)号：US07348245B2

公开(公告)日：2008-03-25

申请号：US11443257

申请日：2006-05-31

申请人： Masaaki Shinohara ,  Kozo Watanabe ,  Fukuo Owada ,  Takashi Aoyama

发明人： Masaaki Shinohara ,  Kozo Watanabe ,  Fukuo Owada ,  Takashi Aoyama

IPC分类号： H01L21/8234

CPC分类号： H01L27/11568 ,  G11C11/005 ,  G11C16/0466 ,  H01L27/105 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： Manufacturing method of a semiconductor device for forming a rewritable nonvolatile memory cell including a first field effect transistor for memory, a circuit including a second field effect transistor and a circuit including a third field effect transistor, including forming a gate insulating film over a semiconductor substrate, a gate electrode over the gate insulating film and sidewall spacers over the sidewalls of the gate electrode associated with each of the first through third field effect transistors. The sidewall spacers of at least the first field effect transistor have a different width than that of at least the second field effect transistor, the gate electrode of the third field effect transistor has a different length than that of at least the first field effect transistor for memory and the gate insulating film of the third field effect transistor has a thickness larger than that of the second field effect transistor.

摘要翻译： 一种半导体器件的制造方法，用于形成包括用于存储器的第一场效应晶体管的可重写非易失性存储单元，包括第二场效应晶体管的电路和包括第三场效应晶体管的电路，包括在半导体衬底上形成栅极绝缘膜 栅极绝缘膜上的栅电极和与第一至第三场效应晶体管中的每一个相关联的栅电极的侧壁上的侧壁隔离物。 至少第一场效应晶体管的侧壁间隔物具有与至少第二场效应晶体管不同的宽度，第三场效应晶体管的栅电极具有与至少第一场效应晶体管不同的长度， 存储器和第三场效应晶体管的栅极绝缘膜的厚度大于第二场效应晶体管的厚度。

公开(公告)号：US20060281007A1

公开(公告)日：2006-12-14

申请号：US10569368

申请日：2005-05-12

申请人： Shuji Tsutsumi ,  Kozo Watanabe ,  Mitsuhiro Takeno ,  Mikinari Shimada

发明人： Shuji Tsutsumi ,  Kozo Watanabe ,  Mitsuhiro Takeno ,  Mikinari Shimada

IPC分类号： H01M2/18 ,  H01M4/58 ,  H01M4/48 ,  H01M10/04

CPC分类号： H01M10/0525 ,  H01M2/18 ,  H01M4/13 ,  H01M4/131 ,  H01M4/133 ,  H01M4/62 ,  H01M10/0587 ,  H01M10/4235 ,  H01M2004/025 ,  Y10T29/49108 ,  Y10T29/49115

摘要： A lithium ion secondary battery with improved safety against both internal short-circuiting and overcharge is provided. This lithium ion secondary battery includes a positive electrode comprising a composite lithium oxide, a negative electrode, and a non-aqueous electrolyte. At least one of the positive electrode and the negative electrode has a porous film, comprising an inorganic oxide filler and a binder, on the surface facing the other electrode, and the electrode surface having the porous film partially has a protruded part. This protruded part may be a protruded part formed on the porous film itself or a protruded part formed on an electrode mixture layer. Further, a separator can also be incorporated therein. Instead of the above-mentioned porous film, the separator can be provided with a porous film.

摘要翻译： 提供一种具有改善内部短路和过充电的安全性的锂离子二次电池。 该锂离子二次电池包括含有复合氧化锂，负极和非水电解质的正极。 正电极和负电极中的至少一个在面向另一个电极的表面上具有包含无机氧化物填充剂和粘合剂的多孔膜，并且具有多孔膜的电极表面部分地具有突出部分。 该突出部分可以是形成在多孔膜本身上的突出部分或形成在电极混合物层上的突出部分。 此外，还可以并入隔板。 代替上述多孔膜，隔板可以设置有多孔膜。