公开(公告)号：US07038282B2

公开(公告)日：2006-05-02

申请号：US10770627

申请日：2004-02-04

申请人： Kei Tokui ,  Hiroshi Iwata ,  Yoshifumi Yaoi ,  Akihide Shibata ,  Masaru Nawaki

发明人： Kei Tokui ,  Hiroshi Iwata ,  Yoshifumi Yaoi ,  Akihide Shibata ,  Masaru Nawaki

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792 ,  H01L29/7923

摘要： A semiconductor storage device includes a voltage supply circuit generating a voltage of 5V, a voltage polarity inversion circuit generating a voltage of −5V, a select-and-connect circuit supplying the voltages of 5V and −5V to a memory cell array, a 5 V voltage level detection circuit detecting the voltage derived from the voltage supply circuit, and a −5 V voltage level detection circuit detecting the voltage derived from the voltage polarity inversion circuit. Absolute values of the voltages detected by the voltage level detection circuits are lower than ever before. This allows a gate insulation film to be thinner. A memory-function film is formed on both sides of a gate electrode in the semiconductor storage device. This also make the gate insulation film thinner. The thin gate insulation film suppresses the short-channel effect, so that each memory element of the memory cell array is miniaturized.

摘要翻译： 半导体存储装置包括产生5V电压的电压供给电路，产生-5V的电压的电压极性反转电路，向存储单元阵列供给5V和-5V的电压的选择和连接电路，5 V电压检测电路，检测从电压供给电路得到的电压;以及-5V电压电平检测电路，检测从电压极性反转电路得到的电压。 由电压电平检测电路检测到的电压的绝对值比以前低。 这允许栅极绝缘膜更薄。 存储功能膜形成在半导体存储装置中的栅电极的两侧。 这也使栅极绝缘膜更薄。 薄栅绝缘膜抑制短沟道效应，使得存储单元阵列的每个存储元件小型化。

公开(公告)号：US20060081941A1

公开(公告)日：2006-04-20

申请号：US11289493

申请日：2005-11-30

申请人： Hiroshi Iwata ,  Akihide Shibata

发明人： Hiroshi Iwata ,  Akihide Shibata

IPC分类号： H01L29/76

CPC分类号： H01L29/66833 ,  B82Y10/00 ,  G11C16/0466 ,  H01L21/84 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/118 ,  H01L27/1203 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor storage device having: a first conductivity type region formed in a semiconductor layer; a second conductivity type region formed in the semiconductor layer in contact with the first conductivity type region; a memory functional element disposed on the semiconductor layer across the boundary of the first and second conductivity type regions; and an electrode provided in contact with the memory functional element and on the first conductivity type region via an insulation film, and a portable electronic apparatus comprising the semiconductor storage device. The present invention can fully cope with scale-down and high-integration by constituting a selectable memory cell substantially of one device.

公开(公告)号：US07009884B2

公开(公告)日：2006-03-07

申请号：US10848260

申请日：2004-05-19

申请人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

发明人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

IPC分类号： G11C16/06

CPC分类号： H01L29/66833 ,  G11C11/5628 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/3454 ,  H01L21/28282 ,  H01L29/792

摘要： A semiconductor storage device includes a memory cell array 21 in which a plurality of memory elements are arranged and a program verify circuit 30. The memory element 1, 33 includes a gate electrode 104 formed on a semiconductor layer 102 via a gate insulator 103, a channel region arranged below the gate electrode 104, diffusion regions 107a, 107b that are located on opposite sides of the channel region and have a conductive type opposite to that of the channel region, and memory function bodies 109 that are located on opposite sides of the gate electrode 104 and have a function of retaining electric charge. A program load register 32 of the program verify circuit 30 eliminates a state that a memory element 33 which has initially been verified as having been correctly programmed needs to be further programmed.

摘要翻译： 半导体存储装置包括其中布置有多个存储元件的存储单元阵列21和程序验证电路30。 存储元件1,33包括通过栅极绝缘体103形成在半导体层102上的栅极电极104，配置在栅电极104下方的沟道区域，位于沟道区域相对侧的扩散区域107a，107b 并且具有与沟道区域相反的导电类型，以及位于栅电极104的相对侧上并具有保持电荷的功能的记忆功能体109。 程序验证电路30的程序加载寄存器32消除了最初被验证为被正确编程的存储元件33需要被进一步编程的状态。

公开(公告)号：US20060044886A1

公开(公告)日：2006-03-02

申请号：US11213927

申请日：2005-08-30

申请人： Hiroshi Iwata ,  Yoshifumi Yaoi ,  Akihide Shibata

发明人： Hiroshi Iwata ,  Yoshifumi Yaoi ,  Akihide Shibata

IPC分类号： G11C5/14

CPC分类号： G11C16/28 ,  G11C7/14

摘要： Characteristic fluctuation of a reference cell due to read disturb is prevented. A memory cell 27m and a reference cell 27r respectively have memory function bodies that are formed on both sides of a gate electrode and have a function to retain electric charge or polarization. The memory cell 27m can store independent information pieces in memory function bodies 27mr and 27ml located on both sides of the gate electrode and the independent information pieces are read therefrom. On the other hand, in the reference cell 27r, only the information piece stored in a memory function body 27rl located on one side of the gate electrode is referred to in a sense amplifier 22.

摘要翻译： 防止由于读取干扰引起的参考单元的特性波动。 存储单元27m和参考单元27r分别具有形成在栅电极的两侧上并具有保持电荷或极化的功能的记忆功能体。 存储单元27m可以将独立的信息块存储在位于栅电极两侧的存储器功能体27mr和27ml中，并从其中读取独立的信息。 另一方面，在参考单元27r中，在读出放大器22中仅参考存储在位于栅电极一侧的存储器功能体27r1中的信息片。

公开(公告)号：US06992933B2

公开(公告)日：2006-01-31

申请号：US10848614

申请日：2004-05-19

申请人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

发明人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

IPC分类号： G11C11/34

CPC分类号： H01L29/66825 ,  G11C11/22 ,  G11C16/0475 ,  G11C16/3431 ,  G11C16/3454 ,  G11C16/3459 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/66833 ,  H01L29/7887

摘要： A method of verifying programming of a nonvolatile memory cell to a desired state, the method comprising the steps of: selecting first and second references respectively corresponding to first and second voltages; applying a programming voltage to the memory cell; sensing a threshold voltage level of the memory cell; and comparing the sensed threshold voltage level with the first and second references and, in the case where the threshold voltage level is higher than the first reference and lower than the second reference, indicating that the memory cell is programmed into the desired state, wherein the nonvolatile memory cell includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region formed below the gate electrode, a source and a drain as diffusion regions formed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.

摘要翻译： 一种将非易失性存储单元的编程验证为期望状态的方法，所述方法包括以下步骤：分别对应于第一和第二电压选择第一和第二参考; 将编程电压施加到所述存储器单元; 感测存储器单元的阈值电压电平; 以及将感测的阈值电压电平与第一和第二参考值进行比较，并且在阈值电压电平高于第一参考值且低于第二参考值的情况下，指示存储器单元被编程到期望状态，其中 非易失性存储单元包括通过栅极绝缘膜形成在半导体层上的栅极电极，形成在栅极电极下方的沟道区域，作为在沟道区域的两侧形成的扩散区域的源极和漏极，并且具有与 沟道区域以及形成在栅电极的两侧上并具有保持电荷功能的存储功能单元。

公开(公告)号：US06990022B2

公开(公告)日：2006-01-24

申请号：US10850212

申请日：2004-05-19

申请人： Yoshinao Morikawa ,  Masaru Nawaki ,  Hiroshi Iwata ,  Akihide Shibata

发明人： Yoshinao Morikawa ,  Masaru Nawaki ,  Hiroshi Iwata ,  Akihide Shibata

IPC分类号： G11C16/04

CPC分类号： H01L29/66833 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  H01L21/28282 ,  H01L29/7923

摘要： A semiconductor memory device includes a memory cell array in which plural memory cells are arranged, a memory operation circuit, connected to the memory cell array, for executing a memory operation on the memory cell array, and a command controller, connected to the memory operation circuit, for receiving a command from the outside and generating a predetermined control signal to the memory operation circuit on the basis of the received command to control execution of the memory operation by the memory operation circuit. The memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.

摘要翻译： 一种半导体存储器件包括其中布置多个存储器单元的存储单元阵列，连接到存储单元阵列的存储器操作电路，用于对存储单元阵列执行存储器操作，以及命令控制器，连接到存储器操作 电路，用于从外部接收指令，并根据接收到的命令产生预定的控制信号到存储器操作电路，以控制存储器操作电路的存储器操作的执行。 存储单元包括通过栅极绝缘膜形成在半导体层上的栅极电极，设置在栅极电极下方的沟道区域，设置在沟道区域两侧并具有与沟道区域相反的导电类型的扩散区域， 以及形成在栅电极的两侧并具有保持电荷的功能的存储功能单元。

公开(公告)号：US20050280065A1

公开(公告)日：2005-12-22

申请号：US11142770

申请日：2005-06-02

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Kotaro Kataoka ,  Masayuki Nakano

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Kotaro Kataoka ,  Masayuki Nakano

IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/792

CPC分类号： H01L29/6684 ,  G11C16/0475 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28291 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7923

摘要： A semiconductor storage device has a single gate electrode formed on a semiconductor substrate through a gate insulation film. First and second memory function bodies formed on both sides of the gate electrode. A P-type channel region is formed in a surface of the substrate on the side of the gate electrode. N-type first and second diffusion regions are formed on both sides of the channel region. The channel region is composed of an offset region located under the first and second memory function bodies and a gate electrode beneath region located under the gate electrode. The concentration of a dopant which imparts a P-type conductivity to the offset region is effectively lower than the concentration of a dopant which imparts the P-type conductivity to the gate electrode beneath region. This makes it possible to provide the semiconductor storage device which is easily shrunk in scale.

摘要翻译： 半导体存储器件具有通过栅极绝缘膜形成在半导体衬底上的单个栅电极。 形成在栅电极两侧的第一和第二记忆功能体。 在栅极侧的基板的表面形成P型沟道区。 在沟道区域的两侧形成N型第一和第二扩散区域。 沟道区域由位于第一和第二存储器功能体之下的偏移区域和位于栅电极下方的栅极电极构成。 赋予偏移区域的P型导电性的掺杂剂的浓度有效地低于向区域下方的栅电极施加P型导电性的掺杂剂的浓度。 这使得可以提供容易缩小的半导体存储装置。

公开(公告)号：US06977843B2

公开(公告)日：2005-12-20

申请号：US10843079

申请日：2004-05-10

申请人： Koji Hamaguchi ,  Masaru Nawaki ,  Yoshinao Morikawa ,  Hiroshi Iwata ,  Akihide Shibata

发明人： Koji Hamaguchi ,  Masaru Nawaki ,  Yoshinao Morikawa ,  Hiroshi Iwata ,  Akihide Shibata

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  G11C16/34 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66833 ,  G11C16/0475 ,  G11C16/30 ,  G11C16/3468 ,  G11C16/3477 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/7887

摘要： A semiconductor memory device has a malfunction prevention device and a nonvolatile memory.The nonvolatile memory is a memory cell including: a gate electrode formed on a semiconductor layer via a gate insulating film; a channel region disposed below the gate electrode; diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region; and memory functional units formed on both sides of the gate electrode and having a function of retaining charges.

摘要翻译： 半导体存储器件具有故障防止装置和非易失性存储器。 非易失性存储器是包括：通过栅极绝缘膜形成在半导体层上的栅电极的存储单元; 设置在所述栅电极下方的沟道区; 扩散区域设置在沟道区域的两侧并且具有与沟道区域的导电类型相反的导电类型; 以及形成在栅电极的两侧并具有保持电荷的功能的记忆功能单元。

公开(公告)号：US06825528B2

公开(公告)日：2004-11-30

申请号：US10149255

申请日：2002-08-12

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto ,  Kouichiro Adachi ,  Masayuki Nakano

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto ,  Kouichiro Adachi ,  Masayuki Nakano

IPC分类号： H01L2976

CPC分类号： H01L29/66628 ,  H01L21/2251 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/78657

摘要： A semiconductor device 1910 comprises a semiconductor substrate 100 including an isolation region 101 and an active region 102, a gate electrode 104 provided on the active region 102 via a gate insulating film 103, part of a side of the gate electrode 104 being covered with a gate electrode side wall insulating film 105, and a source region 106 and a drain region 106 provided on opposite sides of the gate electrode 104 via the gate electrode side wall insulating film 105. At least one of the source region 106 and the drain region 106 has a second surface for contacting a contact conductor. The second surface is tilted with respect to a first surface A-A′. An angle between the second surface and a surface of the isolation region is 80 degrees or less.

摘要翻译： 半导体器件1910包括包括隔离区域101和有源区域102的半导体衬底100，经由栅极绝缘膜103设置在有源区域102上的栅电极104，栅电极104的一侧的一部分被覆盖有 栅电极侧壁绝缘膜105，以及经由栅电极侧壁绝缘膜105设置在栅极电极104的相对侧上的源极区域106和漏极区域106.源极区域106和漏极区域106中的至少一个 具有用于接触接触导体的第二表面。 第二表面相对于第一表面A-A'倾斜。 第二表面与隔离区域的表面之间的角度为80度以下。

公开(公告)号：US06509615B2

公开(公告)日：2003-01-21

申请号：US10067791

申请日：2002-02-08

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto

IPC分类号： H01L31119

CPC分类号： H01L21/76229 ,  H01L21/823807 ,  H01L29/783

摘要： A semiconductor device with dynamic threshold transistors includes a complex element isolation region composed of a shallow element isolation region made of shallow trench isolation and deep element isolation regions provided on both sides of the shallow element isolation region. Since the shallow element isolation region is made of the shallow trench isolation, bird's beak in the shallow element isolation region is small. This prevents off leakage failure due to stress caused by the bird's beak. The deep element isolation region has an approximately constant width which allows the complex element isolation region to be wide.

摘要翻译： 具有动态阈值晶体管的半导体器件包括由浅沟槽隔离构成的浅元件隔离区域和设置在浅元件隔离区域两侧的深元件隔离区域构成的复合元件隔离区域。 由于浅元件隔离区域由浅沟槽隔离构成，浅元件隔离区域中的鸟喙小。 这可以防止由于鸟嘴引起的应力引起的泄漏故障。 深元件隔离区域具有近似恒定的宽度，其允许复杂元件隔离区域宽。