利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

71 条记录 (耗时 0.02 秒)

    PROCESSOR, METHOD AND COMPUTER PROGRAM PRODUCT FOR FAST SELECTIVE INVALIDATION OF TRANSLATION LOOKASIDE BUFFER
    52.
    发明申请
    PROCESSOR, METHOD AND COMPUTER PROGRAM PRODUCT FOR FAST SELECTIVE INVALIDATION OF TRANSLATION LOOKASIDE BUFFER 有权
    处理器，方法和计算机程序产品，用于快速选择性翻译翻译书写缓冲区

    公开(公告)号：US20090216994A1

    公开(公告)日：2009-08-27

    申请号：US12036398

    申请日：2008-02-25

    申请人： Jonathan T. Hsieh ,  Chung-Lung Kevin Shum ,  Charles F. Webb

    发明人： Jonathan T. Hsieh ,  Chung-Lung Kevin Shum ,  Charles F. Webb

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1027

    摘要： A processor including a microarchitecture adapted for invalidating mapping of at least one logical address to at least one absolute address, includes: at least one translation lookaside buffer (TLB) and a plurality of copies thereof; logic for independent indexing of each copy of the TLB; a plurality of comparators, each comparator associated with a respective output of each TLB set output for each TLB port, wherein each of the comparators is adapted for identifying mappings for invalidation; and logic for invalidating each identified mapping. A method and a computer program product are provided.

    摘要翻译： 一种处理器，包括适于使至少一个逻辑地址映射至少一个绝对地址无效的微体系结构，包括：至少一个翻译后备缓冲器（TLB）及其多个副本; 独立索引TLB每份副本的逻辑; 多个比较器，每个比较器与每个TLB端口的每个TLB组输出的相应输出相关联，其中每个比较器适于识别无效化的映射; 以及使每个识别的映射无效的逻辑。 提供了一种方法和计算机程序产品。

    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR AN IMPLICIT PREDICTED RETURN FROM A PREDICTED SUBROUTINE
    53.
    发明申请
    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR AN IMPLICIT PREDICTED RETURN FROM A PREDICTED SUBROUTINE 失效
    方法，系统和计算机程序产品预测从预测的SUBROUTINE返回

    公开(公告)号：US20090210661A1

    公开(公告)日：2009-08-20

    申请号：US12034066

    申请日：2008-02-20

    申请人： Khary J. Alexander ,  James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito ,  Robert J. Sonnelitter, III ,  Charles F. Webb

    发明人： Khary J. Alexander ,  James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito ,  Robert J. Sonnelitter, III ,  Charles F. Webb

    IPC分类号： G06F9/312

    CPC分类号： G06F9/30054 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3844

    摘要： A method, system and computer program product for performing an implicit predicted return from a predicted subroutine are provided. The system includes a branch history table/branch target buffer (BHT/BTB) to hold branch information, including a target address of a predicted subroutine and a branch type. The system also includes instruction buffers, and instruction fetch controls to perform a method including fetching a branch instruction at a branch address and a return-point instruction. The method also includes receiving the target address and the branch type, and fetching a fixed number of instructions in response to the branch type. The method further includes referencing the return-point instruction within the instruction buffers such that the return-point instruction is available upon completing the fetching of the fixed number of instructions absent a re-fetch of the return-point instruction.

    摘要翻译： 提供了一种用于从预测子程序执行隐含预测返回的方法，系统和计算机程序产品。 该系统包括用于保持分支信息的分支历史表/分支目标缓冲器（BHT / BTB），包括预测子程序的目标地址和分支类型。 该系统还包括指令缓冲器和指令获取控制，以执行包括在分支地址和返回点指令处获取分支指令的方法。 该方法还包括接收目标地址和分支类型，以及响应于分支类型取出固定数目的指令。 该方法还包括引用指令缓冲器内的返回点指令，使得在没有重新获取返回点指令的情况下完成取出固定数目的指令后，返回点指令是可用的。

    Register Indirect Access of Program Floating Point Registers by Millicode
    54.
    发明申请
    Register Indirect Access of Program Floating Point Registers by Millicode 失效
    通过Millicode寄存器间接访问程序浮点寄存器

    公开(公告)号：US20080126759A1

    公开(公告)日：2008-05-29

    申请号：US11531301

    申请日：2006-09-13

    申请人： Steven R. Carlough ,  Mark S. Farrell ,  Eric M. Schwarz ,  Timothy J. Slegel ,  Charles F. Webb

    发明人： Steven R. Carlough ,  Mark S. Farrell ,  Eric M. Schwarz ,  Timothy J. Slegel ,  Charles F. Webb

    IPC分类号： G06F9/302

    CPC分类号： G06F9/3017 ,  G06F9/35

    摘要： Complex floating point instructions are executed under millicode control when it is not cost effective to implement its function in hardware. One of the disadvantages to executing complex instructions using millicode routines is that determining and accessing the instructions operands are costly for millicode performance. To determine what the source and target location are, the instruction text is parsed. Furthermore the millicode instruction stream must be modified to access the operand data from and write the result to the program registers specified by the complex floating point instruction. The invention overcomes these disadvantages by providing millicode with register indirect access to the program floating point registers.

    摘要翻译： 当在硬件中实现其功能不具有成本效益时，复杂的浮点指令在毫秒控制下执行。 使用millicode例程执行复杂指令的一个缺点是确定和访问指令操作数对于millicode性能来说是昂贵的。 要确定源和目标位置是什么，解释说明文本。 此外，必须修改millicode指令流以访问操作数数据，并将结果写入由复杂浮点指令指定的程序寄存器。 本发明通过向编程浮点寄存器提供寄存器间接访问的毫代码来克服这些缺点。

    Read only store as part of cache store for storing frequently used millicode instructions
    55.
    发明授权
    Read only store as part of cache store for storing frequently used millicode instructions 失效
    只读存储作为缓存存储的一部分，用于存储常用的millicode指令

    公开(公告)号：US5625808A

    公开(公告)日：1997-04-29

    申请号：US455820

    申请日：1995-05-31

    申请人： Charles F. Webb ,  Mark S. Farrell ,  Barry W. Krumm ,  John S. Liptay ,  Jennifer S. A. Navarro ,  Steven B. Risch ,  Mark A. Check

    发明人： Charles F. Webb ,  Mark S. Farrell ,  Barry W. Krumm ,  John S. Liptay ,  Jennifer S. A. Navarro ,  Steven B. Risch ,  Mark A. Check

    IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F9/22

    CPC分类号： G06F9/3802 ,  G06F9/3017

    摘要： A read only storage (ROS) array holds a small set of relatively simple millicode instructions; those millicode instruction routines which are most commonly called on in executing common application workloads. The millicode read only store is implemented as a portion of hardware system area (HSA) storage. The cache control includes a register which contains hardware system area address corresponding to the read only store address. When an instruction fetch request is received by the cache control, the absolute address of the instruction fetch request is compared with the read only store address in the register in parallel with the normal cache directory lookup. If the instruction fetch request matches the read only store address, the fetch is made from the read only store independently of the directory lookup result.

    摘要翻译： 只读存储（ROS）阵列包含一小组相对简单的millicode指令; 那些在执行常见应用程序工作负载中最常调用的那些millicode指令例程。 millicode只读存储器实现为硬件系统区域（HSA）存储的一部分。 高速缓存控制包括一个寄存器，该寄存器包含与只读存储地址对应的硬件系统区域地址。 当缓存控制接收到指令提取请求时，将指令提取请求的绝对地址与正常缓存目录查找并行地与寄存器中的只读存储地址进行比较。 如果指令提取请求与只读存储地址相匹配，则从独立于目录查找结果的只读存储进行读取。

    Carpet cleaning machine
    56.
    发明授权
    Carpet cleaning machine 失效
    地毯清洗机

    公开(公告)号：US4167799A

    公开(公告)日：1979-09-18

    申请号：US904573

    申请日：1978-05-10

    申请人： Charles F. Webb

    发明人： Charles F. Webb

    IPC分类号： A47L11/34 ,  A47L11/40 ,  A47L7/00

    CPC分类号： A47L11/34 ,  A47L11/4058 ,  A47L11/4066 ,  A47L11/4069 ,  A47L11/4083 ,  A47L11/4086

    摘要： A combination foam and steam carpet cleaning machine incorporating separate storage compartments for the hot water and the foaming liquid, automatic control of vacuum wands positioned ahead and to the rear of the steam jets to permit forward and reverse motion during the steam cleaning operation, individual height adjustments for the cleaning brush and the vacuum wand and spring loading of the vacuum wand to insure adequate pressure of the wand against the carpet for maximum vacuuming efficiency. The machine is self-propelled in both forward and reverse directions.

    摘要翻译： 组合泡沫和蒸汽地毯清洗机，包括用于热水和发泡液体的分离的储存室，自动控制位于蒸汽喷嘴前方和后方的真空棒，以允许在蒸汽清洁操作期间的前进和后退运动，单独的高度 调整清洁刷和真空棒以及真空棒的弹簧加载，以确保魔杖对地毯的足够压力以获得最大的真空效率。 机器在前进和后退方向都是自行推进的。

    Operand fetching control as a function of branch confidence
    57.
    发明授权
    Operand fetching control as a function of branch confidence 有权
    操作数获取控制作为分支置信度的函数

    公开(公告)号：US09411599B2

    公开(公告)日：2016-08-09

    申请号：US12822379

    申请日：2010-06-24

    申请人： Christian Jacobi ,  Barry W. Krumm ,  Brian R. Prasky ,  Martin Recktenwald ,  Chung-Lung K. Shum ,  Charles F. Webb ,  Joshua M. Weinberg

    发明人： Christian Jacobi ,  Barry W. Krumm ,  Brian R. Prasky ,  Martin Recktenwald ,  Chung-Lung K. Shum ,  Charles F. Webb ,  Joshua M. Weinberg

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3824 ,  G06F9/30043 ,  G06F9/3806 ,  G06F9/3844 ,  G06F9/3857

    摘要： Data operand fetching control includes a computer processor that includes a control unit for determining memory access operations. The control unit is configured to perform a method. The method includes calculating a summation weight value for each instruction in a pipeline, the summation weight value calculated as a function of branch uncertainty and a pendency in which the instruction resides in the pipeline relative to other instructions in the pipeline. The method also includes mapping the summation weight value of a selected instruction that is attempting to access system memory to a memory access control, each memory access control specifying a manner of handling data fetching operations. The method further includes performing a memory access operation for the selected instruction based upon the mapping.

    摘要翻译： 数据操作数获取控制包括计算机处理器，其包括用于确定存储器存取操作的控制单元。 控制单元被配置为执行方法。 该方法包括：计算流水线中每个指令的求和权重值，求和作为分支不确定度的函数计算的求和权重值以及相对于流水线中的其他指令，指令驻留在流水线中的挂起。 该方法还包括将尝试访问系统存储器的所选指令的求和权重值映射到存储器访问控制，每个存储器访问控制指定处理数据获取操作的方式。 该方法还包括基于映射执行针对所选择的指令的存储器访问操作。

    Microprocessor, method and computer program product for direct page prefetch in millicode capable computer system
    58.
    发明授权
    Microprocessor, method and computer program product for direct page prefetch in millicode capable computer system 有权
    微处理器，方法和计算机程序产品，用于在具有计算机能力的计算机系统中进行直接页面预取

    公开(公告)号：US08549255B2

    公开(公告)日：2013-10-01

    申请号：US12032041

    申请日：2008-02-15

    申请人： David A. Schroter ,  Mark S. Farrell ,  Jennifer Navarro ,  Chung-Lung Kevin Shum ,  Charles F. Webb

    发明人： David A. Schroter ,  Mark S. Farrell ,  Jennifer Navarro ,  Chung-Lung Kevin Shum ,  Charles F. Webb

    IPC分类号： G06F12/00

    CPC分类号： G06F9/30047 ,  G06F12/0862

    摘要： A microprocessor equipped to provide hardware initiated prefetching, includes at least one architecture for performing: issuance of a prefetch instruction; writing of a prefetch address into a prefetch fetch address register (PFAR); attempting a prefetch according to the address; detecting one of a cache miss and a cache hit; and if there is a cache miss, then sending a miss request to a next cache level and attempting cache access in a non-busy cycle; and if there is a cache hit, then incrementing the address in the PFAR and completing the prefetch. A method and a computer program product are provided.

    摘要翻译： 配备提供硬件发起预取的微处理器包括用于执行：发出预取指令的至少一个架构; 将预取地址写入预取提取地址寄存器（PFAR）; 根据地址尝试预取; 检测缓存未命中和缓存命中之一; 并且如果存在高速缓存未命中，则将错误请求发送到下一个高速缓存级别，并在非繁忙周期中尝试高速缓存访​​问; 并且如果存在缓存命中，则增加PFAR中的地址并完成预取。 提供了一种方法和计算机程序产品。