公开(公告)号：US20050285201A1

公开(公告)日：2005-12-29

申请号：US11217033

申请日：2005-08-31

申请人： Luan Tran

发明人： Luan Tran

IPC分类号： H01L21/8234 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L21/823481 ,  H01L27/10894 ,  H01L27/10897

摘要： Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the active areas having a width of less than one micron, and with some of the active areas having different widths. A gate line is formed over the active areas to provide transistors having different threshold voltages. Preferably, the transistors are provided with different threshold voltages without using a separate channel implant for the transistors. In another embodiment, a plurality of shallow trench isolation regions are formed within a substrate and define a plurality of active areas having widths at least some of which being no greater than about one micron (or less), with some of the widths preferably being different. One or more gate lines may be coupled to the respective active areas to provide individual transistors, with the transistors corresponding to the active areas having the different widths having different threshold voltages. In another embodiment, two field effect transistors are fabricated having different threshold voltages without using a separate channel implant for one of the transistors versus the other.

公开(公告)号：US20050186802A1

公开(公告)日：2005-08-25

申请号：US10783843

申请日：2004-02-20

申请人： Brett Busch ,  Luan Tran ,  Ardavan Niroomand ,  Fred Fishburn ,  Yoshiki Hishiro ,  Ulrich Boettiger ,  Richard Holscher

发明人： Brett Busch ,  Luan Tran ,  Ardavan Niroomand ,  Fred Fishburn ,  Yoshiki Hishiro ,  Ulrich Boettiger ,  Richard Holscher

IPC分类号： H01L21/02 ,  H01L21/033 ,  H01L21/302 ,  H01L21/311 ,  H01L21/461 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L27/10852 ,  H01L28/91 ,  Y10S438/942 ,  Y10S438/946

摘要： A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.

摘要翻译： 图案化掩模可以如下形成。 在掩模层上形成第一图案化的光致抗蚀剂，并在第一蚀刻进入掩模层期间使用。 第一蚀刻延伸到掩模层中的深度不到完全通过掩模层的深度。 随后在掩模层上形成第二图案化的光致抗蚀剂，并在第二次蚀刻进入掩模层期间利用。 组合的第一和第二蚀刻形成完全延伸穿过掩模层的开口，从而在掩模层中形成掩模层。 图案化掩模可以用于在掩模下面的衬底中形成图案。 形成在基板中的图案可以对应于电容器容器开口的阵列。 可以在开口内形成电容结构。 电容器结构可以并入DRAM阵列中。

公开(公告)号：US20050161721A1

公开(公告)日：2005-07-28

申请号：US11072159

申请日：2005-03-04

申请人： Ravi Iyer ,  Yongjun Hu ,  Luan Tran ,  Brent Gilgen

发明人： Ravi Iyer ,  Yongjun Hu ,  Luan Tran ,  Brent Gilgen

IPC分类号： H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L29/45 ,  H01L27/108

CPC分类号： H01L21/76846 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/7687 ,  H01L21/76889 ,  H01L23/485 ,  H01L27/10855 ,  H01L28/84 ,  H01L28/90 ,  H01L29/456 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat. This net migration of the impurities to the first refractory metal material limits growth of a metal silicide interface between the first refractory metal material and the underlying silicon-containing material, thereby providing ohmic contact with attendant thermal tolerance.

摘要翻译： 使用覆盖含硅材料的第一耐火金属材料和覆盖第一难熔金属材料的第二难熔金属材料来降低与含硅材料的接触电阻。 每种难熔金属材料是含有难熔金属和杂质的导电材料。 第一难熔金属材料是富含金属的材料，其含量低于化学计量水平的杂质。 与第一难熔金属材料相比，第二难熔金属材料对杂质的亲和力较低。 因此，第二难熔金属材料可以在退火或其它暴露于热的过程中用作杂质供体。 这种杂质向第一难熔金属材料的净迁移限制了第一难熔金属材料和下面的含硅材料之间的金属硅化物界面的生长，从而提供与耐热性的欧姆接触。

公开(公告)号：US20050056887A1

公开(公告)日：2005-03-17

申请号：US10962665

申请日：2004-10-13

申请人： Luan Tran

发明人： Luan Tran

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10876 ,  H01L27/10808 ,  H01L27/10811 ,  H01L27/10891 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/7834 ,  H01L29/7835

摘要： Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A plurality of columns are defined in an insulating layer formed over the semiconductor substrate subsequent to which a thin sacrificial oxide layer is formed over exposed regions of the semiconductor substrate but not over the field oxide areas. A dielectric material is then provided on sidewalls of each column and over portions of the sacrificial oxide layer and of the field oxide areas. A first etch is conducted to form a first set of trenches within the semiconductor substrate and a plurality of recesses within the field oxide areas. A second etch is conducted to remove dielectric residue remaining on the sidewalls of the columns and to form a second set of trenches. Polysilicon is then deposited within the second set of trenches and within the recesses to form recessed conductive gates.

摘要翻译： 公开了自对准凹陷门结构和形成方法。 首先在半导体衬底中形成用于隔离的场氧化物区域。 多个列限定在形成在半导体衬底上的绝缘层中，接着在半导体衬底的暴露区域上形成薄的牺牲氧化物层，但不在场氧化物区域上。 然后在每列的侧壁和牺牲氧化物层和场氧化物区域的部分上方提供电介质材料。 进行第一蚀刻以在半导体衬底内形成第一组沟槽和在场氧化物区域内形成多个凹陷。 进行第二蚀刻以去除残留在柱的侧壁上的电介质残余物并形成第二组沟槽。 然后将多晶硅沉积在第二组沟槽内并在凹槽内形成凹陷的导电栅极。

公开(公告)号：US06660584B2

公开(公告)日：2003-12-09

申请号：US10056183

申请日：2002-01-24

申请人： Luan Tran

发明人： Luan Tran

IPC分类号： H01L218242

CPC分类号： H01L27/10888 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10885 ,  Y10S257/905 ,  Y10S257/907 ,  Y10S257/908

摘要： A memory cell is defined along first, second, and third orthogonal dimensions and comprises an electrically conductive word line, an electrically conductive bit line, an electrical charge storage structure, a transistor structure, and a bit line contact. The charge storage structure is conductively coupled to the bit line via the transistor structure and the bit line contact. The transistor structure is conductively coupled to the word line. The first dimension is characterized by one-half of a bit line contact feature, one word line feature, one word line space feature, and one-half of a field poly line feature. The second dimension is characterized by two one-half field oxide features and one active area feature. The first and second dimensions define a 6F2 memory cell. The bit line contact feature is characterized by a contact hole bounded by insulating side walls. The insulating side walls comprise a first pair of opposing insulating side walls along the first dimension and a second pair of opposing insulating side walls along the second dimension. The first pair of opposing insulating side walls comprise respective layers of insulating spacer material formed over a conductive line. The second pair of opposing insulating side walls comprise respective layers of insulating material formed between respective contact holes. The contact hole is filled to an uppermost extent of the insulating side walls with a conductively doped polysilicon plug defining a substantially convex upper plug surface profile in contact with the bit line. The memory cell may further comprise a storage node characterized by a storage node contact hole filled with a conductively doped polysilicon plug defining a substantially convex upper plug surface profile.

摘要翻译： 存储单元沿着第一，第二和第三正交尺寸被限定，并且包括导电字线，导电位线，电荷存储结构，晶体管结构和位线接触。 电荷存储结构经由晶体管结构和位线接触导电耦合到位线。 晶体管结构与字线导电耦合。 第一维的特征在于位线接触特征的一半，一个字线特征，一个字线空间特征以及场多边线特征的一半。 第二维度的特征在于两个半场氧化物特征和一个活动区域特征。 第一和第二维定义6F 2存储单元。 位线接触特征的特征在于由绝缘侧壁限定的接触孔。 绝缘侧壁沿着第一尺寸包括第一对相对的绝缘侧壁和沿着第二尺寸的第二对相对绝缘侧壁。 第一对相对的绝缘侧壁包括在导电线上形成的各层绝缘隔离材料。 第二对相对的绝缘侧壁包括在相应的接触孔之间形成的各层绝缘材料。 接触孔用导电掺杂的多晶硅塞填充到绝缘侧壁的最上部，该导电掺杂多晶硅插塞限定与位线接触的基本上凸的上插塞表面轮廓。 存储单元还可以包括存储节点，其特征在于存储节点接触孔，填充有导电掺杂多晶硅插塞，其限定基本上凸起的上插塞表面轮廓。

公开(公告)号：US06410948B1

公开(公告)日：2002-06-25

申请号：US09340983

申请日：1999-06-28

申请人： Luan Tran ,  D. Mark Duncan ,  Tyler A. Lowrey ,  Rob B. Kerr ,  Kris K. Brown

发明人： Luan Tran ,  D. Mark Duncan ,  Tyler A. Lowrey ,  Rob B. Kerr ,  Kris K. Brown

IPC分类号： H01L2710

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L27/10885

摘要： A memory device includes memory cells, bit lines, active area lines running generally in parallel to the bit lines, and transistors formed in each active area line and electrically coupling memory cells to corresponding bit lines. Each bit line includes slanted portions that intersect a corresponding portion of an active area line at an angle. Contacts electrically coupling the bit line to portions of the active area line are formed in a region generally defined by the angled intersection of the bit line to the active area line. The memory cells can have an area of about 6F2, and the bit lines can be coupled to sense amplifiers in a folded bit line configuration. Each bit line includes a first level portion and a second level portion.

摘要翻译： 存储器件包括存储器单元，位线，通常与位线平行地运行的有源区线以及在每个有源区域线中形成的晶体管，并将存储单元电耦合到相应的位线。 每个位线包括以一角度与有源区域线的相应部分相交的倾斜部分。 将位线电耦合到有源区域线的部分的触点形成在通常由位线到有源区域线的成角度的交叉点限定的区域中。 存储器单元可以具有约6F2的面积，并且位线可以以折叠位线配置耦合到读出放大器。 每个位线包括第一电平部分和第二电平部分。

公开(公告)号：US06380576B1

公开(公告)日：2002-04-30

申请号：US09653638

申请日：2000-08-31

申请人： Luan Tran

发明人： Luan Tran

IPC分类号： H01L27108

CPC分类号： H01L27/10888 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10885 ,  Y10S257/905 ,  Y10S257/907 ,  Y10S257/908

摘要： A memory cell is defined along first, second, and third orthogonal dimensions and comprises an electrically conductive word line, an electrically conductive bit line, an electrical charge storage structure, a transistor structure, and a bit line contact. The charge storage structure is conductively coupled to the bit line via the transistor structure and the bit line contact. The transistor structure is conductively coupled to the word line. The first dimension is characterized by one-half of a bit line contact feature, one word line feature, one word line space feature, and one-half of a field poly line feature. The second dimension is characterized by two one-half field oxide features and one active area feature. The first and second dimensions define a 6F2 memory cell. The bit line contact feature is characterized by a contact hole bounded by insulating side walls. The insulating side walls comprise a first pair of opposing insulating side walls along the first dimension and a second pair of opposing insulating side walls along the second dimension. The first pair of opposing insulating side walls comprise respective layers of insulating spacer material formed over a conductive line. The second pair of opposing insulating side walls comprise respective layers of insulating material formed between respective contact holes. The contact hole is filled to an uppermost extent of the insulating side walls with a conductively doped polysilicon plug defining a substantially convex upper plug surface profile in contact with the bit line. The memory cell may further comprise a storage node characterized by a storage node contact hole filled with a conductively doped polysilicon plug defining a substantially convex upper plug surface profile.

公开(公告)号：US20120044735A1

公开(公告)日：2012-02-23

申请号：US13233609

申请日：2011-09-15

申请人： Luan Tran ,  Bill Stanton

发明人： Luan Tran ,  Bill Stanton

IPC分类号： G11C5/06 ,  H01L23/48

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L27/10894 ,  H01L27/11517 ,  Y10S438/942 ,  Y10S438/947

摘要： Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery.

摘要翻译： 提供了方法和结构，用于在将间距倍增的互连线与存储器件中的其它导电特征相接触时增加对准边缘。 存储器件周围的线的部分形成为一角度并相对于存储器件的阵列区域中的线的部分加宽。 当在线上覆盖其他特征（例如着陆垫）时，加宽的线允许增加的误差。 因此，使相邻线路接触和引起电短路的可能性被最小化。 此外，相对于阵列区域中的线的一部分以相对于周边的一部分线形成的部分允许周边部分被加宽，同时还允许多个着陆垫在周边被密集地包装。

公开(公告)号：US07932174B2

公开(公告)日：2011-04-26

申请号：US12333560

申请日：2008-12-12

申请人： Howard E. Rhodes ,  Luan Tran

发明人： Howard E. Rhodes ,  Luan Tran

IPC分类号： H01L21/4763

CPC分类号： H01L27/10894 ,  H01L21/76805 ,  H01L21/76838 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/10808 ,  H01L27/10811 ,  H01L27/10882 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and fabrication process wherein the device includes a conductive layer with a localized thick region positioned below the contact hole. In one embodiment of the invention, the thick region to which contact is made is formed by means of an opening in an underlayer of material. This embodiment of the device includes an underlayer of material having an opening therein; a layer of thin conductive material formed on the underlayer and in the opening; and overlayer of material having a contact hole therethrough formed on the layer of thin conductive material; a conductor contacting the layer of thin conductive material through the contact hole; and wherein the opening in the underlayer is positioned below the contact hole and sized and shaped to form a localized thick region in the layer of thin conductive material within the opening.

摘要翻译： 一种半导体器件和制造工艺，其中该器件包括具有位于接触孔下方的局部厚区域的导电层。 在本发明的一个实施例中，通过材料底层中的开口形成接触的厚区域。 该装置的该实施例包括其中具有开口的材料底层; 形成在底层和开口中的薄导电材料层; 以及在所述薄导电材料层上形成有通孔的材料的覆盖层; 通过所述接触孔与所述薄导电材料层接触的导体; 并且其中所述底层中的开口位于所述接触孔的下方并且其尺寸和形状以在所述开口内的所述薄导电材料层中形成局部厚的区域。

公开(公告)号：US20090087987A1

公开(公告)日：2009-04-02

申请号：US12333560

申请日：2008-12-12

申请人： Howard Rhodes ,  Luan Tran

发明人： Howard Rhodes ,  Luan Tran

IPC分类号： H01L21/768

CPC分类号： H01L27/10894 ,  H01L21/76805 ,  H01L21/76838 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/10808 ,  H01L27/10811 ,  H01L27/10882 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and fabrication process wherein the device includes a conductive layer with a localized thick region positioned below the contact hole. In one embodiment of the invention, the thick region to which contact is made is formed by means of an opening in an underlayer of material. This embodiment of the device includes an underlayer of material having an opening therein; a layer of thin conductive material formed on the underlayer and in the opening; and overlayer of material having a contact hole therethrough formed on the layer of thin conductive material; a conductor contacting the layer of thin conductive material through the contact hole; and wherein the opening in the underlayer is positioned below the contact hole and sized and shaped to form a localized thick region in the layer of thin conductive material within the opening.

摘要翻译： 一种半导体器件和制造工艺，其中该器件包括具有位于接触孔下方的局部厚区域的导电层。 在本发明的一个实施例中，通过材料底层中的开口形成接触的厚区域。 该装置的该实施例包括其中具有开口的材料底层; 形成在底层和开口中的薄导电材料层; 以及在所述薄导电材料层上形成有通孔的材料的覆盖层; 通过所述接触孔与所述薄导电材料层接触的导体; 并且其中所述底层中的开口位于所述接触孔的下方并且其尺寸和形状以在所述开口内的所述薄导电材料层中形成局部厚的区域。