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    FABRICATION OF ELECTRODES FOR MEMORY CELLS
    52.
    发明申请
    FABRICATION OF ELECTRODES FOR MEMORY CELLS 审中-公开

    公开(公告)号：US20190378975A1

    公开(公告)日：2019-12-12

    申请号：US16001795

    申请日：2018-06-06

    Applicant: Micron Technology, Inc.

    Inventor： Pengyuan Zheng ,  Yongjun J. Hu ,  Yao Jin ,  Hongqi Li ,  Andrea Gotti

    IPC: H01L45/00 ,  H01L27/24

    Abstract: Methods, systems, and devices for fabrication of memory cells are described. An electrode layer may have an initial thickness variation after being formed. The electrode layer may be smoothened prior to forming additional layers of a memory cell, thus decreasing the thickness variation. The subsequent layer fabricated may have a thickness variation that may be dependent on the thickness variation of the electrode layer. By decreasing the thickness variation of the electrode layer prior to forming the subsequent layer, the subsequent layer may also have a decreased thickness variation. The decreased thickness variation of the subsequent layer may impact the electrical behavior of memory cells formed from the subsequent layer. In some cases, the decreased thickness variation of the subsequent layer may allow for more predictable voltage thresholds for such memory cells, thus increasing the read windows for the memory cells.

    Semiconductor structures including liners and related methods
    53.
    发明授权
    Semiconductor structures including liners and related methods 有权

    公开(公告)号：US10256406B2

    公开(公告)日：2019-04-09

    申请号：US15155618

    申请日：2016-05-16

    Applicant: Micron Technology, Inc.

    Inventor： Dale W. Collins ,  Andrea Gotti ,  F. Daniel Gealy ,  Tuman E. Allen ,  Swapnil Lengade

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.

    STRUCTURES INCORPORATING AND METHODS OF FORMING METAL LINES INCLUDING CARBON
    54.
    发明申请
    STRUCTURES INCORPORATING AND METHODS OF FORMING METAL LINES INCLUDING CARBON 审中-公开

    公开(公告)号：US20190019947A1

    公开(公告)日：2019-01-17

    申请号：US16121261

    申请日：2018-09-04

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Gotti ,  F. Daniel Gealy ,  Innocenzo Tortorelli ,  Enrico Varesi

    IPC: H01L45/00 ,  H01L27/22 ,  H01L27/24

    Abstract: Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. The memory device additionally comprises a memory cell stack interposed at an intersection between the upper and lower conductive lines. The memory cell stack includes a first active element over the lower conductive line and a second active element over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element. The memory cell stack further includes an electrode interposed between the at least one of the upper and lower conductive lines and the closer of the first and second active elements.

    Memory cells having a number of conductive diffusion barrier materials and manufacturing methods
    57.
    发明授权
    Memory cells having a number of conductive diffusion barrier materials and manufacturing methods 有权
    具有多个导电扩散阻挡材料和制造方法的存储单元

    公开(公告)号：US09130157B2

    公开(公告)日：2015-09-08

    申请号：US13952162

    申请日：2013-07-26

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Gotti ,  F. Daniel Gealy ,  Davide Columbo

    IPC: H01L29/76 ,  H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/12 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1608

    Abstract: Memory cells having a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and a third electrode, and a number of conductive diffusion barrier materials located between a first portion of the memory element and a second portion of the memory element. Memory cells having a select device comprising a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and a third electrode, and a number of conductive diffusion barrier materials located between a first portion of the select device and a second portion of the select device. Manufacturing methods are also described.

    Abstract translation: 具有位于第一电极和第二电极之间的选择器件材料的存储器单元，位于第二电极和第三电极之间的存储元件以及位于存储元件的第一部分和第二电极之间的多个导电扩散阻挡材料 存储元件的一部分。 具有选择装置的存储单元包括位于第一电极和第二电极之间的选择装置材料，位于第二电极和第三电极之间的存储元件以及位于选择器的第一部分之间的多个导电扩散阻挡材料 设备和选择设备的第二部分。 还描述了制造方法。

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